From af28b2d17c0f9e038935867e96f750ecec61aeb7 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 1 Apr 2021 13:10:00 +0100
Subject: [PATCH] add no pll ls180 build

---
 Makefile | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Makefile b/Makefile
index abb446dd..8412997a 100644
--- a/Makefile
+++ b/Makefile
@@ -36,6 +36,12 @@ testgpio_run_sim:
 	python3 src/soc/litex/florent/sim.py --cpu=libresoc \
 			--variant=standardjtagtestgpio
 
+ls180_verilog_nopll:
+	python3 src/soc/simple/issuer_verilog.py \
+	        --debug=jtag --enable-core --disable-pll \
+	        --enable-xics --disable-svp64 \
+			src/soc/litex/florent/libresoc/libresoc.v
+
 ls180_verilog:
 	python3 src/soc/simple/issuer_verilog.py \
 	        --debug=jtag --enable-core --enable-pll \
-- 
2.30.2