From bb8829b357196484ec1278747bc5e0ec608a1ca1 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 10 Jun 2019 05:24:55 +0100 Subject: [PATCH] move FUMemMatchMatrix to mdm module --- src/scoreboard/mdm.py | 22 ++++++++++++++++++++++ src/scoreboard/test_mem2_fu_matrix.py | 18 +----------------- 2 files changed, 23 insertions(+), 17 deletions(-) create mode 100644 src/scoreboard/mdm.py diff --git a/src/scoreboard/mdm.py b/src/scoreboard/mdm.py new file mode 100644 index 00000000..72ac9592 --- /dev/null +++ b/src/scoreboard/mdm.py @@ -0,0 +1,22 @@ +from nmigen.compat.sim import run_simulation +from nmigen.cli import verilog, rtlil +from nmigen import Module + +from scoreboard.fu_reg_matrix import FURegDepMatrix +from scoreboard.addr_match import PartialAddrMatch + +class FUMemMatchMatrix(FURegDepMatrix, PartialAddrMatch): + """ implement a FU-Regs overload with memory-address matching + """ + def __init__(self, n_fu, addrbitwid): + PartialAddrMatch.__init__(self, n_fu, addrbitwid) + FURegDepMatrix.__init__(self, n_fu, n_fu, 1, self.addr_match_o) + + def elaborate(self, platform): + m = Module() + PartialAddrMatch._elaborate(self, m, platform) + FURegDepMatrix._elaborate(self, m, platform) + + return m + + diff --git a/src/scoreboard/test_mem2_fu_matrix.py b/src/scoreboard/test_mem2_fu_matrix.py index de9715e5..4679105e 100644 --- a/src/scoreboard/test_mem2_fu_matrix.py +++ b/src/scoreboard/test_mem2_fu_matrix.py @@ -4,13 +4,11 @@ from nmigen import Module, Const, Signal, Array, Cat, Elaboratable from regfile.regfile import RegFileArray, treereduce from scoreboard.fu_fu_matrix import FUFUDepMatrix -from scoreboard.fu_reg_matrix import FURegDepMatrix from scoreboard.global_pending import GlobalPending from scoreboard.group_picker import GroupPicker from scoreboard.issue_unit import IssueUnitGroup, IssueUnitArray, RegDecode from scoreboard.shadow import ShadowMatrix, BranchSpeculationRecord -from scoreboard.addr_match import PartialAddrMatch - +from scoreboard.mdm import FUMemMatchMatrix from nmutil.latch import SRLatch from nmutil.nmoperator import eq @@ -57,20 +55,6 @@ class MemSim: self.mem[addr>>self.ddepth] = data & ((1<