From cc9d98a1dcc6c307c4a716fab0bbddb11ac9be39 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 28 Feb 2022 17:43:39 +0000 Subject: [PATCH] attempting to introduce an extra few clock cycles delay on power-up this may help with initialisation of I-Cache SRAM which is combinatorial. maybe --- src/soc/simple/issuer.py | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py index 379c373e..cfad831a 100644 --- a/src/soc/simple/issuer.py +++ b/src/soc/simple/issuer.py @@ -436,10 +436,14 @@ class TestIssuerBase(Elaboratable): dbg_sync = ClockDomain(self.dbg_domain) m.domains += dbg_sync + # create a delay, but remember it is in the power-on-reset clock domain! ti_rst = Signal(reset_less=True) delay = Signal(range(4), reset=3) + stop_delay = Signal(range(16), reset=5) with m.If(delay != 0): - m.d.por += delay.eq(delay - 1) + m.d.por += delay.eq(delay - 1) # decrement... in POR domain! + with m.If(stop_delay != 0): + m.d.por += stop_delay.eq(stop_delay - 1) # likewise comb += cd_por.clk.eq(ClockSignal()) # power-on reset delay @@ -450,6 +454,9 @@ class TestIssuerBase(Elaboratable): else: with m.If(delay != 0 | dbg.core_rst_o): comb += core_rst.eq(1) + with m.If(stop_delay != 0): + # run DMI core-stop as well but on an extra couple of cycles + comb += dbg.core_stopped_i.eq(1) # connect external reset signal to DMI Reset if self.dbg_domain != "sync": @@ -815,6 +822,12 @@ class TestIssuerInternal(TestIssuerBase): with m.FSM(name='fetch_fsm'): + # allow fetch to not run at startup due to I-Cache reset not + # having time to settle. power-on-reset holds dbg.core_stopped_i + with m.State("PRE_IDLE"): + with m.If(~dbg.core_stopped_i & ~dbg.core_stop_o): + m.next = "IDLE" + # waiting (zzz) with m.State("IDLE"): # fetch allowed if not failed and stopped but not stepping -- 2.30.2