examples/counter.py

   1 # this file has been generated by sv2nmigen
   2
   3 from nmigen import Signal, Module, Const, Cat, Elaboratable
   4
   5
   6
   7 class up_counter(Elaboratable):
   8
   9     def __init__(self):
  10         #self.clk = Signal() # input
  11         #self.reset = Signal() # input
  12         self.counter = Signal() # output
  13     def elaborate(self, platform=None):
  14         m = Module()
  15         #m.d.comb += self.counter.eq(self.counter_up)
  16         m.d.comb += self.counter.eq(self.counter+1)
  17         return m
  18 #TODO test this on an icestorm compatible FPGA
  19
  20 #module up_counter(input logic clk,
  21 #                  input logic reset,
  22 #                  output[3:0] counter
  23 #                 );
  24 #   reg [3:0] counter_up;
  25 #   // up counter
  26 #   always @(posedge clk or posedge reset)
  27 #     begin
  28 #       if(reset)
  29 #         counter_up <= 4'd0;
  30 #       else
  31 #         counter_up <= counter_up + 4'd1;
  32 #     end
  33 #   assign counter = counter_up;
  34 #endmodule
  35 #