comb assignment now working

[sv2nmigen.git] / examples / assignment.sv

diff --git a/examples/assignment.sv b/examples/assignment.sv
index e3e326e6dc5fd34f80a694225da883c5b2643b54..81831a2cd54fe75751cbd095ef6653471a3ba388 100644 (file)
--- a/examples/assignment.sv
+++ b/examples/assignment.sv
@@ -1,6 +1,6 @@
 module assignment(
-    input i, 
-    output o
+    output o,
+    input i
 );
 assign o = i;
 endmodule