wire assignments

[sv2nmigen.git] / examples / assignment2.sv

diff --git a/examples/assignment2.sv b/examples/assignment2.sv
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+++ b/examples/assignment2.sv
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+module assignment(
+    output o,
+    input i
+);
+wire x,y;
+wire [15:0] z;
+assign x = i;
+assign o = x;
+endmodule