class decl cleanup

[sv2nmigen.git] / examples / test_assignment.py

diff --git a/examples/test_assignment.py b/examples/test_assignment.py
new file mode 100644 (file)
index 0000000..3972ac4
--- /dev/null
+++ b/examples/test_assignment.py
@@ -0,0 +1,22 @@
+from nmigen.compat.sim import run_simulation
+
+import assignment
+
+def tbench(dut):
+    yield dut.i.eq(1)
+    yield
+    yield
+    yield
+    yield dut.i.eq(0)
+    yield
+    yield
+    yield
+
+
+def test_ass():
+    dut = assignment.assignment();
+    run_simulation(dut, tbench(dut), vcd_name="test.vcd")
+
+
+if __name__ == "__main__":
+    test_ass()