+from nmigen.compat.sim import run_simulation
+
+import assignment
+
+def tbench(dut):
+ yield dut.i.eq(1)
+ yield
+ yield
+ yield
+ yield dut.i.eq(0)
+ yield
+ yield
+ yield
+
+
+def test_ass():
+ dut = assignment.assignment();
+ run_simulation(dut, tbench(dut), vcd_name="test.vcd")
+
+
+if __name__ == "__main__":
+ test_ass()