X-Git-Url: https://git.libre-soc.org/?p=sv2nmigen.git;a=blobdiff_plain;f=examples%2Ftest_assignment.py;fp=examples%2Ftest_assignment.py;h=3972ac4855f7a71f6f4b4efde77d5b8735e81057;hp=0000000000000000000000000000000000000000;hb=71d1f25d91fd5bfa2396591c0833dfa56f3f6f3a;hpb=c6580e05691d23f7a69a935801e8e228445deb27

diff --git a/examples/test_assignment.py b/examples/test_assignment.py
new file mode 100644
index 0000000..3972ac4
--- /dev/null
+++ b/examples/test_assignment.py
@@ -0,0 +1,22 @@
+from nmigen.compat.sim import run_simulation
+
+import assignment
+
+def tbench(dut):
+    yield dut.i.eq(1)
+    yield
+    yield
+    yield
+    yield dut.i.eq(0)
+    yield
+    yield
+    yield
+
+
+def test_ass():
+    dut = assignment.assignment();
+    run_simulation(dut, tbench(dut), vcd_name="test.vcd")
+
+
+if __name__ == "__main__":
+    test_ass()