X-Git-Url: https://git.libre-soc.org/?p=sv2nmigen.git;a=blobdiff_plain;f=parse_sv.py;fp=parse_sv.py;h=627aa03121bdb1e073abe7debafe6429b4706820;hp=0c6ad9c6453cd9b558da36e2065a47567aedc424;hb=71d1f25d91fd5bfa2396591c0833dfa56f3f6f3a;hpb=c6580e05691d23f7a69a935801e8e228445deb27 diff --git a/parse_sv.py b/parse_sv.py index 0c6ad9c..627aa03 100644 --- a/parse_sv.py +++ b/parse_sv.py @@ -101,7 +101,7 @@ NP_POUTPUT = 'POUTPUT' NP_PINOUT = 'PINOUT' NP_PREF = 'PREF' -indent = ' ' + class DataType: @@ -4709,7 +4709,7 @@ def p_list_of_port_declarations_1(p): def p_list_of_port_declarations_2(p): '''list_of_port_declarations : list_of_port_declarations ',' port_declaration ''' if(parse_debug): print('list_of_port_declarations_2 FIXME', list(p)) - p[1].append(Leaf(token.NEWLINE, '\n')) # should be a comma + # MOVE_TO absyn p[1].append(Leaf(token.NEWLINE, '\n')) # should be a comma # XXX p[3].prefix=' ' # add a space after the NL, must go in parameter p[1].append(p[3]) p[0] = p[1] @@ -5043,72 +5043,8 @@ def p_cont_assign_list_2(p): def p_module_1(p): '''module : attribute_list_opt module_start lifetime_opt IDENTIFIER _embed0_module module_package_import_list_opt module_parameter_port_list_opt module_port_list_opt module_attribute_foreign ';' _embed1_module timeunits_declaration_opt _embed2_module module_item_list_opt module_end _embed3_module endlabel_opt ''' if(parse_debug>2): print('module_1', list(p)) - absyn.printpy("# module_1") - params = p[7] - clsname = [Leaf(token.NAME, 'class'), - Leaf(token.NAME, p[4], prefix=' '), - Leaf(token.COLON, ':')] - pass_stmt = Node(syms.pass_stmt, [Leaf(token.NAME, "pass"),]) - if params: - params = [Leaf(token.LPAR, '(')] + params + [Leaf(token.RPAR, ')')] - fn = [Leaf(token.NAME, 'def'), - Leaf(token.NAME, '__init__', prefix=' '), - Node(syms.parameters, params), - Leaf(token.COLON, ':')] - fndef = Node(syms.funcdef, fn) - stmts = Node(syms.stmt, [fndef]) - else: - stmts = Node(syms.small_stmt, [pass_stmt, Leaf(token.NEWLINE, '\n')]) - stmts = Node(syms.stmt, [stmts]) - - ports = p[8] - for port in ports: - stmts.children.append(Leaf(token.INDENT, indent*2)) - stmts.children.append(Leaf(token.STRING, port)) - - suite = Node(syms.suite, [Leaf(token.NEWLINE, '\n'), - Leaf(token.INDENT, ' '), - stmts, - Leaf(token.DEDENT, '') - ]) - clsdecl = Node(syms.classdef, clsname + [suite]) - clsdecl = Node(syms.compound_stmt, [clsdecl]) - absyn.printpy("#clsdecl"+ repr(clsdecl)) - absyn.printpy("#clsstr:") - absyn.printpy(str(clsdecl)) + clsdecl = absyn.module_1(p) p[0] = clsdecl - # { // Last step: check any closing name. This is done late so - # // that the parser can look ahead to detect the present - # // endlabel_opt but still have the pform_endmodule() called - # // early enough that the lexor can know we are outside the - # // module. - # if (p[1]7) { - # if (strcmp(p[4],p[1]7) != 0) { - # switch (p[2]) { - # case K_module: - # yyerror(@17, "error: End label doesn't match " - # "module name."); - # break; - # case K_program: - # yyerror(@17, "error: End label doesn't match " - # "program name."); - # break; - # case K_interface: - # yyerror(@17, "error: End label doesn't match " - # "interface name."); - # break; - # default: - # break; - # } - # } - # if ((p[2] == K_module) && (! gn_system_verilog())) { - # yyerror(@8, "error: Module end labels require " - # "SystemVerilog."); - # } - # delete[]p[1]7; - # } - # delete[]p[4]; - # } () def p__embed0_module(p): '''_embed0_module : '''