X-Git-Url: https://git.libre-soc.org/?p=sv2nmigen.git;a=blobdiff_plain;f=parse_sv.py;h=4973540dc4d55dc366c0d1034203623088f90462;hp=28530fcf3c7a1bd96207f8888a1c36c7ccda2b90;hb=e2973c57aa90034c4fb3bff4a1de95b0fd1c9ccc;hpb=1a995ea028ff7f563f1d453f7736bd548120b604 diff --git a/parse_sv.py b/parse_sv.py index 28530fc..4973540 100644 --- a/parse_sv.py +++ b/parse_sv.py @@ -25,7 +25,7 @@ from lib2to3.pygram import python_symbols as syms yacc1_debug = 0 yacc2_debug = 0 -parse_debug = 1 +parse_debug = 0 from ply import yacc, lex @@ -101,14 +101,7 @@ NP_POUTPUT = 'POUTPUT' NP_PINOUT = 'PINOUT' NP_PREF = 'PREF' -def indent(s, i=4): - st = '' - for x in s: - st += str(x) - res = [] - for p in st.split('\n'): - res.append(' ' * i + "#"+p) - return '\n'.join(res) + class DataType: @@ -116,18 +109,6 @@ class DataType: self.typ = typ self.signed = signed -def port_decl(comment, dt, name): - if dt is None or dt.dims is None: - width = '' # width: 1 - else: - width = dt.dims - # XXX TODO, better checking, should be using data structure... *sigh* - width = width[1:-1] # strip brackets - width = width.split(':') - assert width[0] == '0' - width = width[1] - return 'self.%s = Signal(%s) # %s' % (name, width, comment) - # -------------- RULES ---------------- () def p_source_text_1(p): @@ -4716,7 +4697,7 @@ def p_list_of_port_declarations_1(p): def p_list_of_port_declarations_2(p): '''list_of_port_declarations : list_of_port_declarations ',' port_declaration ''' if(parse_debug): print('list_of_port_declarations_2 FIXME', list(p)) - p[1].append(Leaf(token.NEWLINE, '\n')) # should be a comma + # MOVE_TO absyn p[1].append(Leaf(token.NEWLINE, '\n')) # should be a comma # XXX p[3].prefix=' ' # add a space after the NL, must go in parameter p[1].append(p[3]) p[0] = p[1] @@ -4765,9 +4746,8 @@ def p_list_of_port_declarations_5(p): def p_port_declaration_1(p): '''port_declaration : attribute_list_opt K_input net_type_opt data_type_or_implicit IDENTIFIER dimensions_opt ''' if(parse_debug): print('port_declaration_1 FIXME', list(p)) - # XXX TODO: python AST comment, dt, name = p[2], p[4], p[5] - p[0] = port_decl(comment, dt, name) + p[0] = absyn.port_decl(comment, dt, name) # { Module::port_t*ptmp; # perm_string name = lex_strings.make(p[5]); # data_type_t*use_type = p[4]; @@ -4838,9 +4818,8 @@ def p_port_declaration_4(p): def p_port_declaration_5(p): '''port_declaration : attribute_list_opt K_output net_type_opt data_type_or_implicit IDENTIFIER dimensions_opt ''' if(parse_debug): print('port_declaration_5 FIXME', list(p)) - # XXX TODO: python AST comment, dt, name = p[2], p[4], p[5] - p[0] = port_decl(comment, dt, name) + p[0] = absyn.port_decl(comment, dt, name) # { Module::port_t*ptmp; # perm_string name = lex_strings.make(p[5]); # data_type_t*use_dtype = p[4]; @@ -5026,7 +5005,8 @@ def p_lpvalue_4(p): () def p_cont_assign_1(p): '''cont_assign : lpvalue '=' expression ''' - if(parse_debug): print('cont_assign_1 TODO', list(p)) + if(parse_debug): print('cont_assign_1', list(p)) + absyn.cont_assign_1(p) # { list*tmp = new list; # tmp->push_back(p[1]); # tmp->push_back(p[3]); @@ -5050,70 +5030,8 @@ def p_cont_assign_list_2(p): def p_module_1(p): '''module : attribute_list_opt module_start lifetime_opt IDENTIFIER _embed0_module module_package_import_list_opt module_parameter_port_list_opt module_port_list_opt module_attribute_foreign ';' _embed1_module timeunits_declaration_opt _embed2_module module_item_list_opt module_end _embed3_module endlabel_opt ''' if(parse_debug>2): print('module_1', list(p)) - absyn.printpy("# module_1") - params = p[7] - clsname = [Leaf(token.NAME, 'class'), - Leaf(token.NAME, p[4], prefix=' '), - Leaf(token.COLON, ':')] - pass_stmt = Node(syms.pass_stmt, [Leaf(token.NAME, "pass"),]) - if params: - params = [Leaf(token.LPAR, '(')] + params + [Leaf(token.RPAR, ')')] - fn = [Leaf(token.NAME, 'def'), - Leaf(token.NAME, '__init__', prefix=' '), - Node(syms.parameters, params), - Leaf(token.COLON, ':')] - fndef = Node(syms.funcdef, fn) - stmts = Node(syms.stmt, [fndef]) - else: - stmts = Node(syms.small_stmt, [pass_stmt, Leaf(token.NEWLINE, '\n')]) - stmts = Node(syms.stmt, [stmts]) - - # XXX TODO ports as py nodes - ports = p[8] - stmts.children.append(Leaf(token.STRING, '\n' + indent(ports, 8))) - suite = Node(syms.suite, [Leaf(token.NEWLINE, '\n'), - Leaf(token.INDENT, ' '), - stmts, - Leaf(token.DEDENT, '') - ]) - clsdecl = Node(syms.classdef, clsname + [suite]) - clsdecl = Node(syms.compound_stmt, [clsdecl]) - absyn.printpy("#clsdecl"+ repr(clsdecl)) - absyn.printpy("#clsstr:") - absyn.printpy(str(clsdecl)) + clsdecl = absyn.module_1(p) p[0] = clsdecl - # { // Last step: check any closing name. This is done late so - # // that the parser can look ahead to detect the present - # // endlabel_opt but still have the pform_endmodule() called - # // early enough that the lexor can know we are outside the - # // module. - # if (p[1]7) { - # if (strcmp(p[4],p[1]7) != 0) { - # switch (p[2]) { - # case K_module: - # yyerror(@17, "error: End label doesn't match " - # "module name."); - # break; - # case K_program: - # yyerror(@17, "error: End label doesn't match " - # "program name."); - # break; - # case K_interface: - # yyerror(@17, "error: End label doesn't match " - # "interface name."); - # break; - # default: - # break; - # } - # } - # if ((p[2] == K_module) && (! gn_system_verilog())) { - # yyerror(@8, "error: Module end labels require " - # "SystemVerilog."); - # } - # delete[]p[1]7; - # } - # delete[]p[4]; - # } () def p__embed0_module(p): '''_embed0_module : '''