+# this file has been generated by sv2nmigen
+
+from nmigen import Signal, Module, Const, Cat, Elaboratable
+
+
+
+class up_counter(Elaboratable):
+
+ def __init__(self):
+ #self.clk = Signal() # input
+ #self.reset = Signal() # input
+ self.counter = Signal() # output
+ def elaborate(self, platform=None):
+ m = Module()
+ #m.d.comb += self.counter.eq(self.counter_up)
+ m.d.comb += self.counter.eq(self.counter+1)
+ return m
+#TODO test this on an icestorm compatible FPGA
+
+#module up_counter(input logic clk,
+# input logic reset,
+# output[3:0] counter
+# );
+# reg [3:0] counter_up;
+# // up counter
+# always @(posedge clk or posedge reset)
+# begin
+# if(reset)
+# counter_up <= 4'd0;
+# else
+# counter_up <= counter_up + 4'd1;
+# end
+# assign counter = counter_up;
+#endmodule
+#