projects / sv2nmigen.git / tree
? search:
summary | shortlog | log | commit | commitdiff | tree
history | HEAD
cleanup, add example output
[sv2nmigen.git] / examples /
drwxr-xr-x   ..
-rw-r--r-- 351 assignment.py blob | history | raw
-rw-r--r-- 72 assignment.sv blob | history | raw
-rw-r--r-- 872 counter.py blob | history | raw
-rw-r--r-- 341 counter.sv blob | history | raw
-rw-r--r-- 341 test_assignment.py blob | history | raw
automatically converts systemverilog to nmigen