Merge pull request #3310 from robinsonb5-PRs/master
[yosys.git] / kernel /
2022-05-17 Miodrag MilanovićMerge pull request #3310 from robinsonb5-PRs/master master
2022-05-16 Alastair M. RobinsonUse log_warning when Tcl_Init fails, report error with...
2022-05-16 Jannis HarderMerge pull request #3314 from jix/sva_value_change_logi...
2022-05-13 Marcelina KościelnickaAdd opt_ffinv pass.
2022-05-12 Marcelina KościelnickaAdd proc_rom pass.
2022-05-10 Alastair M. RobinsonNow calls Tcl_Init after creating the interp, fixes...
2022-05-09 Jannis HarderMerge pull request #3297 from jix/sva_nested_clk_else
2022-05-09 Miodrag MilanovićMerge pull request #3299 from YosysHQ/mmicko/sim_memory
2022-05-06 Miodrag MilanovicHandle possible non-memory indexed data
2022-05-04 Miodrag Milanovicmap memory location to wire value, if memory is convert...
2022-05-04 Miodrag MilanovicStart restoring memory state from VCD/FST
2022-04-25 Jannis HarderMerge pull request #3287 from jix/smt2-conditional...
2022-04-25 Jannis HarderMerge pull request #3257 from jix/tribuf-formal
2022-04-25 Miodrag MilanovićMerge pull request #3290 from mpasternacki/bugfix/freeb...
2022-04-25 Miodrag MilanovićMerge pull request #3289 from YosysHQ/micko/sim_improve
2022-04-22 Miodrag MilanovicIgnore change on last edge
2022-03-30 Miodrag MilanovićMerge pull request #3259 from YosysHQ/micko/verific_val...
2022-03-30 Miodrag MilanovićMerge pull request #3260 from YosysHQ/micko/proper_scop...
2022-03-30 Miodrag MilanovicProper scope naming from FST
2022-03-30 Miodrag MilanovićMerge pull request #3250 from YosysHQ/micko/verific_con...
2022-03-28 Marcelina Kościelnickakernel/mem: Only use FF init in read-first emu for...
2022-03-28 Jannis HarderMerge pull request #3247 from jix/smtbmc-keepgoing
2022-03-28 LoftyMerge pull request #3194 from Ravenslofty/abc9-flow3mfs
2022-03-28 LoftyMerge pull request #3246 from YosysHQ/gatecat/timing...
2022-03-25 NotAFileAdd some more reserve calls to RTLIL::Const
2022-03-18 Miodrag MilanovicMore verbose warnings
2022-03-17 Miodrag MilanovićMerge pull request #3236 from YosysHQ/micko/tb_initial
2022-03-16 Miodrag MilanovicRecognize registers and set initial state for them...
2022-03-14 Claire XenMerge pull request #3213 from antonblanchard/abc-typo
2022-03-07 Miodrag MilanovićMerge pull request #3210 from rqou/json-signed
2022-03-04 Miodrag MilanovićMerge pull request #3186 from nakengelhardt/smtbmc_sby_...
2022-03-04 Miodrag MilanovićMerge pull request #3206 from YosysHQ/micko/quote_remove
2022-03-04 Miodrag MilanovićMerge pull request #3207 from nakengelhardt/json_escape...
2022-03-04 Miodrag MilanovićMerge pull request #3219 from YosysHQ/micko/quick_vcd
2022-02-28 Miodrag MilanovicVCD reader support by using external tool
2022-02-28 Miodrag MilanovićMerge pull request #3216 from YosysHQ/claire/simstuff
2022-02-25 Miodrag MilanovicFix for last clock edge data
2022-02-22 Claire XenMerge pull request #3211 from YosysHQ/micko/witness
2022-02-22 Claire XenMerge pull request #3197 from YosysHQ/claire/smtbmcfix
2022-02-21 Miodrag MilanovićMerge pull request #3203 from YosysHQ/micko/sim_ff
2022-02-18 Miodrag MilanovicChanged error message
2022-02-16 Miodrag MilanovicAdd support for various ff/latch cells simulation
2022-02-11 Claire XenMerge pull request #2376 from nmoroze/clk2ff-better...
2022-02-11 Miodrag MilanovićMerge pull request #3164 from zachjs/fix-ast-warn
2022-02-11 Claire XenMerge branch 'master' into clk2ff-better-names
2022-02-11 Claire XenMerge pull request #2019 from boqwxp/glift
2022-02-07 Miodrag MilanovićMerge pull request #3185 from YosysHQ/micko/co_sim
2022-02-04 Miodrag MilanovicError detection for co-simulation
2022-02-04 Miodrag Milanovicbug fix and cleanups
2022-01-31 Miodrag MilanovicCleanup
2022-01-31 Miodrag MilanovicDisplay simulation time data
2022-01-28 Marcelina KościelnickaAdd $bmux and $demux cells.
2022-01-28 Miodrag Milanovicignore not found private signals
2022-01-28 Miodrag Milanovicpreserve VCD mangled names
2022-01-28 Miodrag Milanovicdetect edges even when x
2022-01-28 Miodrag Milanoviccleanup
2022-01-28 Miodrag MilanovicDo actual compare
2022-01-28 Miodrag MilanovicAdd more options and time handling
2022-01-28 Marcelina Kościelnickakernel/mem: Add read-first semantic emulation code.
2022-01-27 Marcelina Kościelnickakernel/mem: Add functions to emulate read port enable...
2022-01-26 Miodrag MilanovicFix tabs/spaces
2022-01-26 Miodrag MilanovicAdd fstdata helper class
2022-01-19 Miodrag MilanovićMerge pull request #3120 from Icenowy/anlogic-bram
2022-01-17 N. EngelhardtMerge pull request #3145 from nakengelhardt/advertise_s...
2022-01-04 Zachary Snowlogger: fix unmatched expected warnings and errors
2021-12-16 CatherineMerge pull request #3115 from whitequark/issue-3112
2021-12-16 CatherineMerge pull request #3114 from whitequark/issue-3113
2021-12-14 CatherineMerge pull request #3111 from whitequark/issue-3110
2021-12-14 Claire Xenia WolfHotfix for run_shell auto-detection
2021-12-14 CatherineFix null pointer dereference after failing to extract...
2021-12-12 CatherineMerge pull request #3105 from whitequark/cxxrtl-reset...
2021-12-12 Marcelina KościelnickaFix unused param warning with ENABLE_NDEBUG.
2021-12-10 Miodrag MilanovićMerge pull request #3097 from YosysHQ/modport
2021-12-10 Claire XenMerge pull request #3099 from YosysHQ/claire/readargs
2021-12-09 Claire Xenia WolfAdded "yosys -r <topmodule>"
2021-12-09 Claire Xenia WolfUse "read" command to parse HDL files from Yosys comman...
2021-11-25 Loftysta: very crude static timing analysis pass
2021-11-05 Miodrag MilanovicMake it work on all
2021-11-05 Miodrag MilanovićMerge pull request #3067 from YosysHQ/aki/ci_update
2021-11-05 Miodrag MilanovicRemoved semicolon from macro
2021-10-27 Marcelina Kościelnickadfflegalize: Refactor, add aldff support.
2021-10-26 Zachary Snowverilog: use derived module info to elaborate cell...
2021-10-26 Rupert SwarbrickSplit out logic for reprocessing an AstModule
2021-10-21 Marcelina KościelnickaChange implicit conversions from bool to Sig* to explicit.
2021-10-11 Claire XenMerge pull request #3039 from YosysHQ/claire/verific_aldff
2021-10-08 Marcelina KościelnickaFix a regression from #3035.
2021-10-07 Marcelina KościelnickaFfData: some refactoring.
2021-10-02 Marcelina KościelnickaHook up $aldff support in various passes.
2021-10-02 Marcelina Kościelnickakernel/ff: Refactor FfData to enable FFs with async...
2021-10-02 Marcelina KościelnickaAdd $aldff and $aldffe: flip-flops with async load.
2021-10-02 Marcelina Kościelnickasimplemap: refactor to use FfData.
2021-09-10 Miodrag MilanovićMerge pull request #3001 from YosysHQ/claire/sigcheck
2021-09-10 Claire Xenia WolfAdd additional check to SigSpec
2021-08-16 Marcelina Kościelnickakernel/mem: Remove old parameter when upgrading $mem...
2021-08-13 Rupert SwarbrickGenerate an RTLIL representation of bind constructs
2021-08-13 Miodrag MilanovićMerge pull request #2932 from YosysHQ/mwk/logger-check...
2021-08-12 Marcelina Kościelnickalogger: Add -check-expected subcommand.
2021-08-11 Marcelina KościelnickaAdd v2 memory cells.
2021-08-10 Marcelina Kościelnickakernel/mem: Introduce transparency masks.
2021-08-09 Marcelina KościelnickaRefactor common parts of SAT-using optimizations into...
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