Merge pull request #3310 from robinsonb5-PRs/master
[yosys.git] / techlibs /
2022-04-25 Rick LuikenAdd missing parameters for ecp5
2022-03-30 Miodrag MilanovićMerge pull request #3250 from YosysHQ/micko/verific_con...
2022-03-28 Jannis HarderMerge pull request #3253 from jix/smtbmc-nodeepcopy
2022-03-28 Jannis HarderMerge pull request #3247 from jix/smtbmc-keepgoing
2022-03-28 LoftyMerge pull request #3194 from Ravenslofty/abc9-flow3mfs
2022-03-28 LoftyMerge pull request #3246 from YosysHQ/gatecat/timing...
2022-03-28 Tim Pamborgowin: Add oscillator primitives
2022-03-21 Marcelina Kościelnickaxilinx: Add RAMB4* blackboxes
2022-03-14 YRabbitgowin: add support for Double Data Rate primitives
2022-03-14 Claire XenMerge pull request #3213 from antonblanchard/abc-typo
2022-03-11 Miodrag MilanovićMerge pull request #3228 from YosysHQ/micko/disable_tests
2022-03-11 Miodrag MilanovićMerge pull request #3226 from YosysHQ/micko/btor2witness
2022-03-09 Loftyintel_alm: M10K write-enable is negative-true
2022-03-07 Miodrag MilanovićMerge pull request #3210 from rqou/json-signed
2022-03-04 Miodrag MilanovićMerge pull request #3186 from nakengelhardt/smtbmc_sby_...
2022-03-04 Miodrag MilanovićMerge pull request #3206 from YosysHQ/micko/quote_remove
2022-03-04 Miodrag MilanovićMerge pull request #3207 from nakengelhardt/json_escape...
2022-02-24 YRabbitgowin: Remove unnecessary attributes
2022-02-24 YRabbitgowin: Add support for true differential output
2022-02-22 Claire XenMerge pull request #3211 from YosysHQ/micko/witness
2022-02-22 Claire XenMerge pull request #3197 from YosysHQ/claire/smtbmcfix
2022-02-21 Miodrag MilanovićMerge pull request #3203 from YosysHQ/micko/sim_ff
2022-02-21 Marcelina Kościelnickaecp5: Do not use specify in generate in cells_sim.v.
2022-02-12 Marcelina Kościelnickagowin: Add remaining block RAM blackboxes.
2022-02-11 Miodrag MilanovićMerge pull request #3164 from zachjs/fix-ast-warn
2022-02-11 Claire XenMerge branch 'master' into clk2ff-better-names
2022-02-11 Claire XenMerge pull request #2019 from boqwxp/glift
2022-02-09 Miodrag MilanovićMerge pull request #3193 from YosysHQ/micko/verific_f
2022-02-09 Marcelina Kościelnickagowin: Fix LUT RAM inference, add more models.
2022-02-09 Marcelina Kościelnickaecp5: Fix DPR16X4 sim model.
2022-02-07 Miodrag MilanovićMerge pull request #3185 from YosysHQ/micko/co_sim
2022-02-06 Marcelina Kościelnickanexus: Fix arith_map CO signal.
2022-01-31 Miodrag MilanovićMerge pull request #3176 from higuoxing/fix-ref-manual
2022-01-30 Xing GUOFix the help message of synth_quicklogic.
2022-01-28 Marcelina KościelnickaAdd $bmux and $demux cells.
2022-01-19 gatecatnexus: Fix BB sim model
2022-01-19 Miodrag MilanovicRemoved dbits 8 since 9 will always be picked
2022-01-19 Miodrag MilanovićMerge pull request #3120 from Icenowy/anlogic-bram
2021-12-25 CatherineMerge pull request #3127 from whitequark/cxxrtl-no...
2021-12-21 Loftyintel_alm: disable 256x40 M10K mode
2021-12-17 Icenowy Zhenganlogic: support BRAM mapping
2021-11-25 Loftyintel_alm: preliminary Arria V support
2021-11-13 Patrick Urbansynth_gatemate Revert cascade A/B port mixup
2021-11-13 Patrick Urbansynth_gatemate: Remove iob_map invokation
2021-11-13 Patrick Urbansynth_gatemate: Add block RAM cascade support
2021-11-13 Patrick Urbansynth_gatemate: Remove obsolete iob_map
2021-11-13 Patrick Urbansynth_gatemate: Update pass
2021-11-13 Patrick Urbansynth_gatemate: Remove specify blocks
2021-11-13 Patrick Urbansynth_gatemate: Remove gatemate_bramopt pass
2021-11-13 Patrick Urbansynth_gatemate: Revise block RAM read modes and initial...
2021-11-13 Patrick Urbansynth_gatemate: Remove unsupported FF initialization
2021-11-13 Patrick Urbansynth_gatemate: Rename multiplier factor parameters
2021-11-13 Patrick Urbansynth_gatemate: Registers are uninitialized
2021-11-13 Patrick Urbansynth_gatemate: Apply review remarks
2021-11-13 Patrick Urbansynth_gatemate: Apply review remarks
2021-11-13 Patrick Urbansynth_gatemate: Initial implementation
2021-11-10 Claire XenMerge pull request #3077 from YosysHQ/claire/genlib
2021-11-09 Marcelina Kościelnickaiopadmap: Add native support for negative-polarity...
2021-11-07 Pepijn de Vossynth_gowin: move splitnets to after iopadmap (#2435)
2021-11-07 Pepijn de VosRemove noalu from synth_gowin json output as Apicula...
2021-11-06 Pepijn de Vosgowin: widelut support (#3042)
2021-10-27 Miodrag MilanovićMerge pull request #3063 from YosysHQ/micko/verific_aldff
2021-10-27 Marcelina Kościelnickaecp5: Add support for mapping aldff.
2021-10-19 Claire Xenia WolfFixed Verific parser error in ice40 cell library
2021-10-19 Miodrag MilanovićMerge pull request #3045 from galibert/master
2021-10-17 Olivier GalibertCycloneV: Add (passthrough) support for cyclonev_oscillator
2021-10-17 Olivier GalibertCycloneV: Add (passthrough) support for cyclonev_hps_in...
2021-10-02 Marcelina KościelnickaHook up $aldff support in various passes.
2021-10-02 Marcelina KościelnickaAdd $aldff and $aldffe: flip-flops with async load.
2021-09-09 Eddie Hungabc9: replace cell type/parameters if derived type...
2021-08-29 kittennbfive[ECP5] fix wrong link for syn_* attributes description...
2021-08-22 ECP5-PCIeAdd DLLDELD
2021-08-20 Pepijn de VosGowin: deal with active-low tristate (#2971)
2021-08-17 Sylvain Munautice40: Fix typo in SB_CARRY specify for LP/UltraPlus
2021-08-11 Marcelina KościelnickaAdd v2 memory cells.
2021-07-30 Maciej DudekFixes xc7 BRAM36s
2021-07-29 Marcelina Kościelnickaopt_lut: Allow more than one -dlogic per cell type.
2021-07-28 Marcelina Kościelnickamemory: Introduce $meminit_v2 cell, with EN input.
2021-07-10 Marcelina Kościelnickaice40: Fix LUT input indices in opt_lut -dlogic (again).
2021-07-06 gatecatecp5: Add DCSC blackbox
2021-06-09 Claire XenMerge pull request #2817 from YosysHQ/claire/fixemails
2021-06-09 Claire Xenia WolfFix icestorm links
2021-06-09 Claire Xenia WolfUse HTTPS for website links, gatecat email
2021-06-09 Claire Xenia WolfFix files with CRLF line endings
2021-06-07 Claire Xenia WolfFixing old e-mail addresses and deadnames
2021-05-15 gatecatintel_alm: Fix illegal carry chains
2021-05-15 gatecatintel_alm: Add global buffer insertion
2021-05-15 gatecatintel_alm: Add IO buffer insertion
2021-05-12 Adam GreigAdd missing parameters for MULT18X18D and ALU54B to...
2021-04-27 Miodrag MilanovićMerge pull request #2738 from mdko/xilinx-blif
2021-04-27 Michael ChristensenFix use of blif name in synth_xilinx command
2021-04-21 Claire XenMerge pull request #2669 from YosysHQ/claire/ice40defaults
2021-04-20 Claire Xenia WolfAdd default assignments to other SB_* simulation models
2021-04-20 Claire Xenia WolfAdd default assignments to SB_LUT4
2021-04-17 Loftyquicklogic: ABC9 synthesis
2021-04-09 Stefan Riesenbergersf2: fix name of AND modules ls180
2021-03-30 Eddie Hungabc9: fix SCC issues (#2694)
2021-03-19 Miodrag MilanovićMerge pull request #2681 from msinger/fix-issue2606
2021-03-18 Loftyquicklogic: PolarPro 3 support
2021-03-17 gatecatBlackbox all whiteboxes after synthesis
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