2 .
/ls180soc.py
--build
--platform
=ls180sram4k
--num-srams
=2
3 cp build
/ls180sram4k
/gateware
/ls180sram4k.v .
/ls180.v
4 cp build
/ls180sram4k
/gateware
/mem.init .
5 cp build
/ls180sram4k
/gateware
/mem_1.init .
6 cp libresoc
/libresoc.v .
7 yosys
-p
'read_verilog libresoc.v' \
8 -p
'write_ilang libresoc_cvt.il'
9 yosys
-p
'read_verilog ls180.v' \
10 -p
'read_verilog SPBlock_512W64B8W.v' \
11 -p
'write_ilang ls180_cvt.il'
12 yosys
-p
'read_ilang ls180_cvt.il' \
13 -p
'read_ilang libresoc_cvt.il' \
14 -p
'write_ilang ls180.il'
17 .
/ls180soc.py
--build
--platform
=ls180
--num-srams
=2
18 cp build
/ls180
/gateware
/ls180.v .
19 cp build
/ls180
/gateware
/mem.init .
20 cp build
/ls180
/gateware
/mem_1.init .
21 cp libresoc
/libresoc.v .
22 yosys
-p
'read_verilog libresoc.v' \
23 -p
'read_verilog ls180.v' \
25 -p
'write_verilog ls180_cvt.v'
26 yosys
-p
'read_verilog ls180.v' \
27 -p
'read_verilog SPBlock_512W64B8W.v' \
28 -p
'write_ilang ls180_cvt.il'
29 yosys
-p
'read_verilog libresoc.v' \
30 -p
'write_ilang libresoc_cvt.il'
31 yosys
-p
'read_verilog ls180.v' \
32 -p
'read_verilog SPBlock_512W64B8W.v' \
33 -p
'write_ilang ls180_cvt.il'
34 yosys
-p
'read_ilang ls180_cvt.il' \
35 -p
'read_ilang libresoc_cvt.il' \
36 -p
'write_ilang ls180.il'
39 .
/versa_ecp5.py
--sys-clk-freq
=55e6
--build
42 .
/versa_ecp5.py
--sys-clk-freq
=55e6
--load