update to build ls180 4k SRAMs

diff --git a/Makefile b/Makefile
index 5ea2421f41bf213e7564b0b61c08ef4d7b653b77..622960dd466939e3c3f4bf6bda2ad48537ce0eea 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -21,6 +21,7 @@ ls180:
        cp libresoc/libresoc.v .
        yosys -p 'read_verilog libresoc.v' \
              -p 'read_verilog ls180.v' \
+             -p 'proc' \
           -p 'write_verilog ls180_cvt.v'
        yosys -p 'read_verilog ls180.v' \
              -p 'read_verilog SPBlock_512W64B8W.v' \

diff --git a/ls180soc.py b/ls180soc.py
index 8e54d5e7537b502b4c3fcab71d1c419f18f9c8c3..26e18ba3a8be287072f0da36974b5be093bef016 100755 (executable)
--- a/ls180soc.py
+++ b/ls180soc.py
@@ -43,6 +43,7 @@ from microwatt import Microwatt
 # HACK!
 from litex.soc.integration.soc import SoCCSRHandler
 SoCCSRHandler.supported_address_width.append(12)
+SoCCSRHandler.supported_address_width.append(13)
 
 # GPIO Tristate -------------------------------------------------------
 # doesn't work properly.
@@ -298,7 +299,7 @@ class LibreSoCSim(SoCCore):
             irq_reserved_irqs = {'uart': 0},
             platform='sim',
             dff_srams=5,
-            srams_4k=4,
+            srams_4k=False,
             ):
         assert cpu in ["libresoc", "microwatt"]
         sys_clk_freq = int(50e6)
@@ -315,7 +316,12 @@ class LibreSoCSim(SoCCore):
         #cpu_data_width = 32
         cpu_data_width = 64
 
-        variant = "ls180nopll"
+        if srams_4k:
+            variant = "ls180sram4k"
+        else:
+            variant = "ls180nopll"
+
+        print ("CPU, variant", platform_name, variant)
 
         # reserve XICS ICP and XICS memory addresses.
         self.mem_map['icp']  = 0xc0010000
@@ -363,7 +369,7 @@ class LibreSoCSim(SoCCore):
             cpu_cls                  = LibreSoC   if cpu == "libresoc" \
                                        else Microwatt,
             #bus_data_width           = 64, # don't add this! stops conversion
-            csr_address_width        = 14, # limit to 0x8000
+            csr_address_width        = 13, # limit to 0x8000
             cpu_variant              = variant,
             csr_data_width            = 8,
             l2_size             = 0,
@@ -871,14 +877,18 @@ def main():
                         help="Cycle to end FST tracing")
     parser.add_argument("--num-srams",    default=5,
                         help="number of srams")
+    parser.add_argument("--srams4k",    action="store_true",
+                        help="enable 4k srams")
     parser.add_argument("--build", action="store_true", help="Build bitstream")
     args = parser.parse_args()
 
     print ("number of SRAMs", args.num_srams)
+    print ("enable 4K SRAMs variant", args.srams4k)
 
     if 'ls180' in args.platform:
         soc = LibreSoCSim(cpu=args.cpu, debug=args.debug,
                           platform=args.platform,
+                          srams_4k=args.srams4k,
                           dff_srams=args.num_srams)
         builder = Builder(soc, compile_gateware = True)
         builder.build(run         = True)

diff --git a/versa_ecp5.py b/versa_ecp5.py
index 487c96bda45ead1ce313cdd6a05928f5304f02f1..18aca0eedf6f9f8ab3ecffa5fd6e98d305e92376 100755 (executable)
--- a/versa_ecp5.py
+++ b/versa_ecp5.py
@@ -14,6 +14,11 @@ from litex.soc.integration.builder import (Builder, builder_args,
 from libresoc import LibreSoC
 #from microwatt import Microwatt
 
+# HACK!
+from litex.soc.integration.soc import SoCCSRHandler
+SoCCSRHandler.supported_address_width.append(12)
+
+
 # TestSoC
 # ----------------------------------------------------------------------------
 
@@ -24,6 +29,7 @@ class VersaECP5TestSoC(versa_ecp5.BaseSoC):
         kwargs["integrated_rom_size"] = 0x10000
         #kwargs["integrated_main_ram_size"] = 0x1000
         kwargs["csr_data_width"] = 32
+        kwargs['csr_address_width'] = 12 # limit to 0x8000
         kwargs["l2_size"] = 0
         #bus_data_width = 16,