2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
6 use work.decode_types.all;
9 use work.insn_helpers.all;
13 EX1_BYPASS : boolean := true;
14 HAS_FPU : boolean := true;
15 -- Non-zero to enable log data collection
16 LOG_LENGTH : natural := 0
22 complete_in : in std_ulogic;
23 busy_in : in std_ulogic;
24 stall_out : out std_ulogic;
26 stopped_out : out std_ulogic;
28 flush_in: in std_ulogic;
30 d_in : in Decode1ToDecode2Type;
32 e_out : out Decode2ToExecute1Type;
34 r_in : in RegisterFileToDecode2Type;
35 r_out : out Decode2ToRegisterFileType;
37 c_in : in CrFileToDecode2Type;
38 c_out : out Decode2ToCrFileType;
40 log_out : out std_ulogic_vector(9 downto 0)
44 architecture behaviour of decode2 is
45 type reg_type is record
46 e : Decode2ToExecute1Type;
50 signal r, rin : reg_type;
52 signal deferred : std_ulogic;
54 type decode_input_reg_t is record
55 reg_valid : std_ulogic;
57 data : std_ulogic_vector(63 downto 0);
60 type decode_output_reg_t is record
61 reg_valid : std_ulogic;
65 function decode_input_reg_a (t : input_reg_a_t; insn_in : std_ulogic_vector(31 downto 0);
66 reg_data : std_ulogic_vector(63 downto 0);
68 instr_addr : std_ulogic_vector(63 downto 0))
69 return decode_input_reg_t is
71 if t = RA or (t = RA_OR_ZERO and insn_ra(insn_in) /= "00000") then
72 return ('1', gpr_to_gspr(insn_ra(insn_in)), reg_data);
74 -- ISPR must be either a valid fast SPR number or all 0 for a slow SPR.
75 -- If it's all 0, we don't treat it as a dependency as slow SPRs
76 -- operations are single issue.
78 assert is_fast_spr(ispr) = '1' or ispr = "0000000"
79 report "Decode A says SPR but ISPR is invalid:" &
80 to_hstring(ispr) severity failure;
81 return (is_fast_spr(ispr), ispr, reg_data);
83 return ('0', (others => '0'), instr_addr);
84 elsif HAS_FPU and t = FRA then
85 return ('1', fpr_to_gspr(insn_fra(insn_in)), reg_data);
87 return ('0', (others => '0'), (others => '0'));
91 function decode_input_reg_b (t : input_reg_b_t; insn_in : std_ulogic_vector(31 downto 0);
92 reg_data : std_ulogic_vector(63 downto 0);
93 ispr : gspr_index_t) return decode_input_reg_t is
94 variable ret : decode_input_reg_t;
98 ret := ('1', gpr_to_gspr(insn_rb(insn_in)), reg_data);
101 ret := ('1', fpr_to_gspr(insn_frb(insn_in)), reg_data);
103 ret := ('0', (others => '0'), (others => '0'));
106 ret := ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_ui(insn_in)), 64)));
108 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)), 64)));
110 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)) & x"0000", 64)));
112 ret := ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_si(insn_in)) & x"0000", 64)));
114 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_li(insn_in)) & "00", 64)));
116 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_bd(insn_in)) & "00", 64)));
118 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_ds(insn_in)) & "00", 64)));
120 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_dq(insn_in)) & "0000", 64)));
122 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_dx(insn_in)) & x"0004", 64)));
124 ret := ('0', (others => '0'), x"FFFFFFFFFFFFFFFF");
126 ret := ('0', (others => '0'), x"00000000000000" & "00" & insn_in(1) & insn_in(15 downto 11));
128 ret := ('0', (others => '0'), x"00000000000000" & "000" & insn_in(15 downto 11));
130 -- ISPR must be either a valid fast SPR number or all 0 for a slow SPR.
131 -- If it's all 0, we don't treat it as a dependency as slow SPRs
132 -- operations are single issue.
133 assert is_fast_spr(ispr) = '1' or ispr = "0000000"
134 report "Decode B says SPR but ISPR is invalid:" &
135 to_hstring(ispr) severity failure;
136 ret := (is_fast_spr(ispr), ispr, reg_data);
138 ret := ('0', (others => '0'), (others => '0'));
144 function decode_input_reg_c (t : input_reg_c_t; insn_in : std_ulogic_vector(31 downto 0);
145 reg_data : std_ulogic_vector(63 downto 0)) return decode_input_reg_t is
149 return ('1', gpr_to_gspr(insn_rs(insn_in)), reg_data);
151 return ('1', gpr_to_gspr(insn_rcreg(insn_in)), reg_data);
154 return ('1', fpr_to_gspr(insn_frt(insn_in)), reg_data);
156 return ('0', (others => '0'), (others => '0'));
160 return ('1', fpr_to_gspr(insn_frc(insn_in)), reg_data);
162 return ('0', (others => '0'), (others => '0'));
165 return ('0', (others => '0'), (others => '0'));
169 function decode_output_reg (t : output_reg_a_t; insn_in : std_ulogic_vector(31 downto 0);
170 ispr : gspr_index_t) return decode_output_reg_t is
174 return ('1', gpr_to_gspr(insn_rt(insn_in)));
176 return ('1', gpr_to_gspr(insn_ra(insn_in)));
179 return ('1', fpr_to_gspr(insn_frt(insn_in)));
181 return ('0', "0000000");
184 -- ISPR must be either a valid fast SPR number or all 0 for a slow SPR.
185 -- If it's all 0, we don't treat it as a dependency as slow SPRs
186 -- operations are single issue.
187 assert is_fast_spr(ispr) = '1' or ispr = "0000000"
188 report "Decode B says SPR but ISPR is invalid:" &
189 to_hstring(ispr) severity failure;
190 return (is_fast_spr(ispr), ispr);
192 return ('0', "0000000");
196 function decode_rc (t : rc_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic is
200 return insn_rc(insn_in);
208 -- For now, use "rc" in the decode table to decide whether oe exists.
209 -- This is not entirely correct architecturally: For mulhd and
210 -- mulhdu, the OE field is reserved. It remains to be seen what an
211 -- actual POWER9 does if we set it on those instructions, for now we
212 -- test that further down when assigning to the multiplier oe input.
214 function decode_oe (t : rc_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic is
218 return insn_oe(insn_in);
224 -- control signals that are derived from insn_type
225 type mux_select_array_t is array(insn_type_t) of std_ulogic_vector(2 downto 0);
227 constant result_select : mux_select_array_t := (
228 OP_AND => "001", -- logical_result
238 OP_RLC => "010", -- rotator_result
243 OP_EXTSWSLI => "010",
244 OP_MUL_L64 => "011", -- muldiv_result
250 OP_CNTZ => "100", -- countzero_result
251 OP_MFSPR => "101", -- spr_result
252 OP_ADDG6S => "111", -- misc_result
258 others => "000" -- default to adder_result
261 constant subresult_select : mux_select_array_t := (
262 OP_MUL_L64 => "000", -- muldiv_result
268 OP_ADDG6S => "001", -- misc_result
277 -- issue control signals
278 signal control_valid_in : std_ulogic;
279 signal control_valid_out : std_ulogic;
280 signal control_stall_out : std_ulogic;
281 signal control_sgl_pipe : std_logic;
283 signal gpr_write_valid : std_ulogic;
284 signal gpr_write : gspr_index_t;
285 signal gpr_bypassable : std_ulogic;
287 signal update_gpr_write_valid : std_ulogic;
288 signal update_gpr_write_reg : gspr_index_t;
290 signal gpr_a_read_valid : std_ulogic;
291 signal gpr_a_read :gspr_index_t;
292 signal gpr_a_bypass : std_ulogic;
294 signal gpr_b_read_valid : std_ulogic;
295 signal gpr_b_read : gspr_index_t;
296 signal gpr_b_bypass : std_ulogic;
298 signal gpr_c_read_valid : std_ulogic;
299 signal gpr_c_read : gspr_index_t;
300 signal gpr_c_bypass : std_ulogic;
302 signal cr_write_valid : std_ulogic;
303 signal cr_bypass : std_ulogic;
304 signal cr_bypass_avail : std_ulogic;
307 control_0: entity work.control
315 complete_in => complete_in,
316 valid_in => control_valid_in,
317 repeated => r.repeat,
319 deferred => deferred,
320 flush_in => flush_in,
321 sgl_pipe_in => control_sgl_pipe,
322 stop_mark_in => d_in.stop_mark,
324 gpr_write_valid_in => gpr_write_valid,
325 gpr_write_in => gpr_write,
326 gpr_bypassable => gpr_bypassable,
328 update_gpr_write_valid => update_gpr_write_valid,
329 update_gpr_write_reg => update_gpr_write_reg,
331 gpr_a_read_valid_in => gpr_a_read_valid,
332 gpr_a_read_in => gpr_a_read,
334 gpr_b_read_valid_in => gpr_b_read_valid,
335 gpr_b_read_in => gpr_b_read,
337 gpr_c_read_valid_in => gpr_c_read_valid,
338 gpr_c_read_in => gpr_c_read,
340 cr_read_in => d_in.decode.input_cr,
341 cr_write_in => cr_write_valid,
342 cr_bypass => cr_bypass,
343 cr_bypassable => cr_bypass_avail,
345 valid_out => control_valid_out,
346 stall_out => control_stall_out,
347 stopped_out => stopped_out,
349 gpr_bypass_a => gpr_a_bypass,
350 gpr_bypass_b => gpr_b_bypass,
351 gpr_bypass_c => gpr_c_bypass
354 deferred <= r.e.valid and busy_in;
356 decode2_0: process(clk)
358 if rising_edge(clk) then
359 if rst = '1' or flush_in = '1' or deferred = '0' then
360 if rin.e.valid = '1' then
361 report "execute " & to_hstring(rin.e.nia);
368 c_out.read <= d_in.decode.input_cr;
370 decode2_1: process(all)
371 variable v : reg_type;
372 variable mul_a : std_ulogic_vector(63 downto 0);
373 variable mul_b : std_ulogic_vector(63 downto 0);
374 variable decoded_reg_a : decode_input_reg_t;
375 variable decoded_reg_b : decode_input_reg_t;
376 variable decoded_reg_c : decode_input_reg_t;
377 variable decoded_reg_o : decode_output_reg_t;
378 variable length : std_ulogic_vector(3 downto 0);
382 v.e := Decode2ToExecute1Init;
384 mul_a := (others => '0');
385 mul_b := (others => '0');
387 --v.e.input_cr := d_in.decode.input_cr;
388 v.e.output_cr := d_in.decode.output_cr;
390 decoded_reg_a := decode_input_reg_a (d_in.decode.input_reg_a, d_in.insn, r_in.read1_data, d_in.ispr1,
392 decoded_reg_b := decode_input_reg_b (d_in.decode.input_reg_b, d_in.insn, r_in.read2_data, d_in.ispr2);
393 decoded_reg_c := decode_input_reg_c (d_in.decode.input_reg_c, d_in.insn, r_in.read3_data);
394 decoded_reg_o := decode_output_reg (d_in.decode.output_reg_a, d_in.insn, d_in.ispr1);
396 if d_in.decode.repeat /= NONE then
398 v.e.second := r.repeat;
399 case d_in.decode.repeat is
401 -- do RS|1,RS for LE; RS,RS|1 for BE
402 if r.repeat = d_in.big_endian then
403 decoded_reg_c.reg(0) := '1';
406 -- do RT|1,RT for LE; RT,RT|1 for BE
407 if r.repeat = d_in.big_endian then
408 decoded_reg_o.reg(0) := '1';
414 r_out.read1_enable <= decoded_reg_a.reg_valid and d_in.valid;
415 r_out.read1_reg <= decoded_reg_a.reg;
416 r_out.read2_enable <= decoded_reg_b.reg_valid and d_in.valid;
417 r_out.read2_reg <= decoded_reg_b.reg;
418 r_out.read3_enable <= decoded_reg_c.reg_valid and d_in.valid;
419 r_out.read3_reg <= decoded_reg_c.reg;
421 case d_in.decode.length is
436 v.e.unit := d_in.decode.unit;
437 v.e.fac := d_in.decode.facility;
438 v.e.insn_type := d_in.decode.insn_type;
439 v.e.read_reg1 := decoded_reg_a.reg;
440 v.e.read_data1 := decoded_reg_a.data;
441 v.e.bypass_data1 := gpr_a_bypass;
442 v.e.read_reg2 := decoded_reg_b.reg;
443 v.e.read_data2 := decoded_reg_b.data;
444 v.e.bypass_data2 := gpr_b_bypass;
445 v.e.read_data3 := decoded_reg_c.data;
446 v.e.bypass_data3 := gpr_c_bypass;
447 v.e.write_reg := decoded_reg_o.reg;
448 v.e.write_reg_enable := decoded_reg_o.reg_valid;
449 v.e.rc := decode_rc(d_in.decode.rc, d_in.insn);
450 if not (d_in.decode.insn_type = OP_MUL_H32 or d_in.decode.insn_type = OP_MUL_H64) then
451 v.e.oe := decode_oe(d_in.decode.rc, d_in.insn);
453 v.e.cr := c_in.read_cr_data;
454 v.e.bypass_cr := cr_bypass;
455 v.e.xerc := c_in.read_xerc_data;
456 v.e.invert_a := d_in.decode.invert_a;
458 if d_in.decode.insn_type = OP_BC or d_in.decode.insn_type = OP_BCREG then
461 if d_in.insn(23) = '1' or
462 (d_in.decode.insn_type = OP_BCREG and d_in.insn(10) = '0') then
463 -- don't write decremented CTR if BO(2) = 1 or bcctr
464 v.e.write_reg_enable := '0';
467 v.e.invert_out := d_in.decode.invert_out;
468 v.e.input_carry := d_in.decode.input_carry;
469 v.e.output_carry := d_in.decode.output_carry;
470 v.e.is_32bit := d_in.decode.is_32bit;
471 v.e.is_signed := d_in.decode.is_signed;
472 if d_in.decode.lr = '1' then
473 v.e.lr := insn_lk(d_in.insn);
475 v.e.insn := d_in.insn;
476 v.e.data_len := length;
477 v.e.byte_reverse := d_in.decode.byte_reverse;
478 v.e.sign_extend := d_in.decode.sign_extend;
479 v.e.update := d_in.decode.update;
480 v.e.reserve := d_in.decode.reserve;
481 v.e.br_pred := d_in.br_pred;
482 v.e.result_sel := result_select(d_in.decode.insn_type);
483 v.e.sub_select := subresult_select(d_in.decode.insn_type);
486 control_valid_in <= d_in.valid;
487 control_sgl_pipe <= d_in.decode.sgl_pipe;
489 gpr_write_valid <= v.e.write_reg_enable;
490 gpr_write <= decoded_reg_o.reg;
491 gpr_bypassable <= '0';
492 if EX1_BYPASS and d_in.decode.unit = ALU then
493 gpr_bypassable <= '1';
495 update_gpr_write_valid <= d_in.decode.update;
496 update_gpr_write_reg <= decoded_reg_a.reg;
498 -- there are no instructions that have both update=1 and lr=1
499 update_gpr_write_valid <= '1';
500 update_gpr_write_reg <= fast_spr_num(SPR_LR);
503 gpr_a_read_valid <= decoded_reg_a.reg_valid;
504 gpr_a_read <= decoded_reg_a.reg;
506 gpr_b_read_valid <= decoded_reg_b.reg_valid;
507 gpr_b_read <= decoded_reg_b.reg;
509 gpr_c_read_valid <= decoded_reg_c.reg_valid;
510 gpr_c_read <= decoded_reg_c.reg;
512 cr_write_valid <= d_in.decode.output_cr or decode_rc(d_in.decode.rc, d_in.insn);
513 cr_bypass_avail <= '0';
514 if EX1_BYPASS and d_in.decode.unit = ALU then
515 cr_bypass_avail <= d_in.decode.output_cr;
518 v.e.valid := control_valid_out;
519 if control_valid_out = '1' then
520 v.repeat := v.e.repeat and not r.repeat;
523 stall_out <= control_stall_out or v.repeat;
525 if rst = '1' or flush_in = '1' then
526 v.e := Decode2ToExecute1Init;
537 d2_log: if LOG_LENGTH > 0 generate
538 signal log_data : std_ulogic_vector(9 downto 0);
540 dec2_log : process(clk)
542 if rising_edge(clk) then
543 log_data <= r.e.nia(5 downto 2) &
555 end architecture behaviour;