examples/firmware/main.c

   1 #include <stdlib.h>
   2 #include <stdint.h>
   3 #include <gram.h>
   4
   5 static inline uint32_t read32(const void *addr)
   6 {
   7         return *(volatile uint32_t *)addr;
   8 }
   9
  10 static inline void write32(void *addr, uint32_t value)
  11 {
  12         *(volatile uint32_t *)addr = value;
  13 }
  14
  15 struct uart_regs {
  16         uint32_t divisor;
  17         uint32_t rx_data;
  18         uint32_t rx_rdy;
  19         uint32_t rx_err;
  20         uint32_t tx_data;
  21         uint32_t tx_rdy;
  22         uint32_t zero0; // reserved
  23         uint32_t zero1; // reserved
  24         uint32_t ev_status;
  25         uint32_t ev_pending;
  26         uint32_t ev_enable;
  27 };
  28
  29 void uart_write(char c)
  30 {
  31         struct uart_regs *regs = 0x2000;
  32         while (!read32(&regs->tx_rdy));
  33         write32(&regs->tx_data, c);
  34 }
  35
  36 void uart_writestr(const char *c) {
  37         while (*c) {
  38                 uart_write(*c);
  39                 c++;
  40         }
  41 }
  42
  43 void memcpy(void *dest, void *src, size_t n) {
  44    int i;
  45    //cast src and dest to char*
  46    char *src_char = (char *)src;
  47    char *dest_char = (char *)dest;
  48    for (i=0; i<n; i++)
  49           dest_char[i] = src_char[i]; //copy contents byte by byte
  50 }
  51
  52 void uart_writeuint32(uint32_t val) {
  53         const char lut[] = { '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F' };
  54         uint8_t *val_arr = &val;
  55         size_t i;
  56
  57         for (i = 0; i < 4; i++) {
  58                 uart_write(lut[(val_arr[3-i] >> 4) & 0xF]);
  59                 uart_write(lut[val_arr[3-i] & 0xF]);
  60         }
  61 }
  62
  63 void isr(void) {
  64
  65 }
  66
  67 int main(void) {
  68         const int kNumIterations = 65536;
  69         int res, failcnt = 0;
  70         uint32_t tmp;
  71         volatile uint32_t *ram = 0x10000000;
  72         uart_writestr("Firmware launched...\n");
  73
  74         uart_writestr("DRAM init... ");
  75         struct gramCtx ctx;
  76         struct gramProfile profile = {
  77                 .mode_registers = {
  78                         0x320, 0x6, 0x200, 0x0
  79                 },
  80                 .rdly_p0 = 2,
  81                 .rdly_p1 = 2,
  82         };
  83         struct gramProfile profile2;
  84         gram_init(&ctx, &profile, (void*)0x10000000, (void*)0x00009000, (void*)0x00008000);
  85         uart_writestr("done\n");
  86
  87         uart_writestr("Rdly\np0: ");
  88         for (size_t i = 0; i < 8; i++) {
  89                 profile2.rdly_p0 = i;
  90                 gram_load_calibration(&ctx, &profile2);
  91                 gram_reset_burstdet(&ctx);
  92                 for (size_t j = 0; j < 128; j++) {
  93                         tmp = ram[j];
  94                 }
  95                 if (gram_read_burstdet(&ctx, 0)) {
  96                         uart_writestr("1");
  97                 } else {
  98                         uart_writestr("0");
  99                 }
 100         }
 101         uart_writestr("\n");
 102
 103         uart_writestr("Rdly\np1: ");
 104         for (size_t i = 0; i < 8; i++) {
 105                 profile2.rdly_p1 = i;
 106                 gram_load_calibration(&ctx, &profile2);
 107                 gram_reset_burstdet(&ctx);
 108                 for (size_t j = 0; j < 128; j++) {
 109                         tmp = ram[j];
 110                 }
 111                 if (gram_read_burstdet(&ctx, 1)) {
 112                         uart_writestr("1");
 113                 } else {
 114                         uart_writestr("0");
 115                 }
 116         }
 117         uart_writestr("\n");
 118
 119         uart_writestr("Auto calibrating... ");
 120         res = gram_generate_calibration(&ctx, &profile2);
 121         if (res != GRAM_ERR_NONE) {
 122                 uart_writestr("failed\n");
 123                 gram_load_calibration(&ctx, &profile);
 124         } else {
 125                 gram_load_calibration(&ctx, &profile2);
 126         }
 127         uart_writestr("done\n");
 128
 129         uart_writestr("Auto calibration profile:");
 130         uart_writestr("p0 rdly:");
 131         uart_writeuint32(profile2.rdly_p0);
 132         uart_writestr(" p1 rdly:");
 133         uart_writeuint32(profile2.rdly_p1);
 134         uart_writestr("\n");
 135
 136         uart_writestr("DRAM test... \n");
 137         for (size_t i = 0; i < kNumIterations; i++) {
 138                 ram[i] = 0xDEAF0000 | i*4;
 139         }
 140
 141         for (size_t i = 0; i < kNumIterations; i++) {
 142                 if (ram[i] != (0xDEAF0000 | i*4)) {
 143                         uart_writestr("fail : *(0x");
 144                         uart_writeuint32(&ram[i]);
 145                         uart_writestr(") = ");
 146                         uart_writeuint32(ram[i]);
 147                         uart_write('\n');
 148                         failcnt++;
 149
 150                         if (failcnt > 10) {
 151                                 uart_writestr("Test canceled (more than 10 errors)\n");
 152                                 break;
 153                         }
 154                 }
 155         }
 156         uart_writestr("done\n");
 157
 158         while (1);
 159
 160         return 0;
 161 }