gram.git
2023-05-21 Andrey Miroshnikovsetup.py: Removed deps as per bug #1086#c7. master
2023-05-17 Cesar StraussAvoid depending on a newer setuptool version
2022-07-23 Cesar StraussRemove unused Minerva CPU import from headless examples
2022-07-23 Cesar StraussDo not invert DDR3 CS pin on Icarus testbench
2022-07-23 Cesar StraussUse DELAYG instead of DELAYF on Icarus simulation
2022-07-23 Cesar StraussMerge runsimsoc2.sh into runsimsoc.sh
2022-04-15 Luke Kenneth... remove pyvcd dependency, it is pulled in by nmigen...
2022-04-15 Luke Kenneth... add features option to gramCore and PHY wishbone buses...
2022-04-15 Luke Kenneth... fix reset to be xdr=4x in ECP5DDRPHY
2022-04-15 Luke Kenneth... connect (new) reset signal on IOPads which comes from...
2022-04-14 Luke Kenneth... whilst IOpads and PLLs were driving from dramsync,...
2022-04-10 Raptor Engineering... Don't reset the core / peripherals on DRAM controller...
2022-04-10 Raptor Engineering... Put sysclk2x back under system reset control
2022-04-09 Raptor Engineering... Avoid timing violation on ECP5 PHY PAUSE signal
2022-04-09 Raptor Engineering... Revert "Avoid timing violation on ECP5 PHY PAUSE signal"
2022-04-09 Raptor Engineering... Avoid timing violation on ECP5 PHY PAUSE signal
2022-04-09 Raptor Engineering... Wire up missing CRG / DDR3 clock control / reset signals
2022-04-07 Raptor Engineering... Re-apply part of 180026c72f0e1d3ef365b2214288d4a543a238dd
2022-04-07 Raptor Engineering... Backport litedram 05ed5bf59d31029d3f91c5a348cdd539a150631b
2022-04-07 Raptor Engineering... Working at 50MHz system clock
2022-04-07 Raptor Engineering... Switch CRG back over to ECP5 version
2022-04-07 Raptor Engineering... Partially revert GIT hash 180026c72f0e1d3ef365b2214288d...
2022-04-07 Raptor Engineering... Properly connect reset and cs signals
2022-04-07 Raptor Engineering... Add initial support for external DRAM init on the Rapto...
2022-03-17 Luke Kenneth... initialise bitslip with a specific value rather than...
2022-03-17 Luke Kenneth... add alternative variant of runsimsoc.sh
2022-03-13 Luke Kenneth... add 1024M_ddr3_parameters.vh for MT41K64M16
2022-03-11 Luke Kenneth... add a 2nd clock, this one deliberately the
2022-03-11 Luke Kenneth... annoyingly reverting reset_n naming back to reset
2022-03-10 Luke Kenneth... tidyup on gramWishbone class, add comments
2022-03-10 Luke Kenneth... tidy up gramWishbone constructor, pass Wishbone feature...
2022-03-10 Luke Kenneth... code-cleanup and copyright notices
2022-03-01 Luke Kenneth... fix up simulation to be more like VERSA_ECP5
2022-02-28 Luke Kenneth... remove unneeded import
2022-02-26 Luke Kenneth... use dict for lookup of DFI to pads names
2022-02-26 Luke Kenneth... add missing reset-HI values to cas_n, cs_n, we_n and...
2022-02-25 Luke Kenneth... get chipselect (cs_n) name right in ECP5DDRPHY
2022-02-25 Luke Kenneth... restore naming convention "cs_r" on DFI Interface
2022-02-25 Luke Kenneth... set name of DFI interface to ecp5phy in ECP5DDRPHY
2022-02-25 Luke Kenneth... allow DDR3 reset (rst) signal to be controlled by DFI...
2022-02-24 Luke Kenneth... add a BitSlip module
2022-02-24 Luke Kenneth... replace the simulation Clock-Reset-Generator with one...
2022-02-24 Luke Kenneth... add CSRs to FakePHY which allows at least testing of...
2022-02-22 Luke Kenneth... remove continue/skip and add comment that all
2022-02-21 Luke Kenneth... add debug print statements to investigate FakePHY
2022-02-21 Luke Kenneth... add a debug verilog dump of one of the FakePHY SocTest...
2022-02-20 Luke Kenneth... add dfii submodules so they get explicit names
2022-02-20 Luke Kenneth... add name to DFI Interface (helps gtkwave traces)
2022-02-19 Luke Kenneth... fix gram unit test imports
2022-02-16 Luke Kenneth... fix ECP5DDRPHY cs declaration
2020-08-07 Jean THOMASgram.test.test_core_bankmachine: Reduce formal test...
2020-08-07 Jean THOMASAdd links to other memory controller projects
2020-08-07 Jean THOMASgram.core.multiplexer: Fix variable name in _Steerer
2020-08-07 Jean THOMASgram.test.test_core_multiplexer: Add test for _Steerer...
2020-08-07 Jean THOMASgram.core.multiplexer: Remove unnecessary array slicing
2020-08-07 Jean THOMASgram.core.multiplexer: Code cleaning in _Steerer
2020-08-07 Jean THOMASgram.core.multiplexer: Cleaner code in _Steerer
2020-08-07 Jean THOMASexamples: Display rdly map
2020-08-07 Jean THOMASgram.test.test_core_bankmachine: Ensure refresh_gnt...
2020-08-07 Jean THOMASgram.core.bankmachine: Make condition code cleaner
2020-08-07 Jean THOMASgram.core.bankmachine: Add comment for address slicers
2020-08-07 Jean THOMASgram.core.bankmachine: Remove unused local variables...
2020-08-07 Jean THOMASgram.core.bankmachine: Rename LiteDRAM -> gram in docum...
2020-08-07 Jean THOMASgram.test.test_core_bankmachine: Add test for _AddressS...
2020-08-07 Jean THOMASgram.test.test_core_refresher: Add test for ZQCSExecute...
2020-08-07 Jean THOMASgram.phy.ecp5ddrphy: Fix ECP5DDRPHYInit (wrong domains)
2020-08-07 Jean THOMASgram.phy.ecp5ddrphy: Remove internal signal for delay
2020-08-07 Jean THOMASgram.phy.ecp5ddrphy: Detect burstdet on rising edge...
2020-08-06 Jean THOMASexamples: Load stock calibration profile if calibration...
2020-08-06 Jean THOMASgram.phy.ecp5ddrphy: Make non-critical signals reset...
2020-08-06 Jean THOMASgram.phy.ecp5ddrphy: Revert to LiteDRAM's dqs_re
2020-08-06 Jean THOMASgram.core.multiplexer: Fix regression introduced in...
2020-08-06 Jean THOMASexamples: Make frequency a parameter
2020-08-06 Jean THOMASexamples: Continue self-test even if calibration is...
2020-08-06 Jean THOMASgram.phy.ecp5ddrphy: Remove unused stream import
2020-08-06 Jean THOMASgram.phy.ecp5ddrphy: Add documentation for _DQSBUFMSett...
2020-08-06 Jean THOMASgram.test: Use correct timing for simulations
2020-08-06 Jean THOMASgram.phy.ecp5ddrphy: Fix DQSBUFM's pause signal (fixes...
2020-08-06 Jean THOMASgram.phy.ecp5ddrphy: Code cleaning
2020-08-05 Jean THOMASgram.core.bankmachine: Factorize tXXDController valid...
2020-08-05 Jean THOMASFix code styling
2020-08-05 Jean THOMASRemove steerer_sel function
2020-08-05 Jean THOMASFix test using delays for comb propagation instead...
2020-08-05 Jean THOMASAdd unit test for tXXDController
2020-08-04 Jean THOMASFix AntiStarvation test
2020-08-04 Jean THOMASFix exception condition
2020-08-04 Jean THOMASRaise ValueError if the number of DQ pads is not a...
2020-08-04 Jean THOMASRaise ValueError if RefreshTimer period is unsupported...
2020-08-04 Jean THOMASRaise ValueError if anti-starvation timeout is unsuppor...
2020-08-04 Jean THOMASRaise ValueError if commands array isn't of len=4 ...
2020-08-04 Jean THOMASSample data based on datavalid signal (fixes #47)
2020-08-04 Jean THOMASRaise exception if no native port is present (fixing...
2020-08-04 Jean THOMASMake burstdet_reg reset-less
2020-08-04 Jean THOMASFix simulation to support diff pairs
2020-08-04 Jean THOMASFix sel signal used in wishbone frontend
2020-08-04 Jean THOMASDefault SEL to 1's if SEL=0 (fixes #43)
2020-08-04 Jean THOMASRemove unused variable in wishbone frontend test
2020-08-03 Jean THOMASAdd additional tests for sel signal
2020-08-03 Jean THOMASAdd more sel tests
2020-08-03 Jean THOMASFix native port we signal (fixes #44)
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