Properly connect reset and cs signals

Starting to get (corrupt) data out of the memory...

diff --git a/examples/headless-versa-85.py b/examples/headless-versa-85.py
index 3254115e99ea70e5b9ee0a9856b952f412cd8ee3..24cb4d01b440345bcbc148d9a3fbb164350c5e68 100644 (file)
--- a/examples/headless-versa-85.py
+++ b/examples/headless-versa-85.py
@@ -19,7 +19,8 @@ from gram.modules import MT41K64M16
 from gram.frontend.wishbone import gramWishbone
 
 from nmigen_boards.versa_ecp5 import VersaECP5Platform85
-from ecp5_crg import ECP5CRG
+#from ecp5_crg import ECP5CRG
+from crg import ECPIX5CRG
 from uartbridge import UARTBridge
 from crg import *
 
@@ -30,12 +31,13 @@ class DDR3SoC(SoC, Elaboratable):
         self._decoder = wishbone.Decoder(addr_width=30, data_width=32, granularity=8,
                                          features={"cti", "bte"})
 
-        self.crg = ECP5CRG()
+        self.crg = ECPIX5CRG()
+        #self.crg = ECP5CRG()
 
         self.ub = UARTBridge(divisor=868, pins=platform.request("uart", 0))
 
         ddr_pins = platform.request("ddr3", 0, dir={"dq":"-", "dqs":"-"},
-            xdr={"clk":4, "a":4, "ba":4, "clk_en":4, "odt":4, "ras":4, "cas":4, "we":4, "cs":4, "reset":4})
+            xdr={"clk":4, "a":4, "ba":4, "clk_en":4, "odt":4, "ras":4, "cas":4, "we":4, "cs":4, "rst":1})
         self.ddrphy = DomainRenamer("dramsync")(ECP5DDRPHY(ddr_pins))
         self._decoder.add(self.ddrphy.bus, addr=ddrphy_addr)
 

diff --git a/examples/headless/main.c b/examples/headless/main.c
index bc3e98afc201ad877ff7f6bd09b22a56077a96f6..35e6b46a3a8fddf434582135c6b03700988d84c2 100644 (file)
--- a/examples/headless/main.c
+++ b/examples/headless/main.c
@@ -110,16 +110,25 @@ int main(int argc, char *argv[]) {
 
        uint32_t ddr_base = 0x10000000;
 
-#if 1
+#if 0
        struct gramProfile profile = {
                .mode_registers = {
-                       0x2708, 0x2054, 0x0512, 0x0000
+                       0xb30, 0x806, 0x200, 0x0
                },
                .rdly_p0 = 2,
                .rdly_p1 = 2,
        };
 #endif
 #if 0
+       struct gramProfile profile = {
+               .mode_registers = {
+                       0xb20, 0x806, 0x200, 0x0
+               },
+               .rdly_p0 = 2,
+               .rdly_p1 = 2,
+       };
+#endif
+#if 1
        struct gramProfile profile = {
                .mode_registers = {
                        0x320, 0x6, 0x200, 0x0
@@ -149,6 +158,7 @@ int main(int argc, char *argv[]) {
        gram_init(&ctx, &profile, (void*)ddr_base, (void*)0x00009000, (void*)0x00008000);
        printf("done\n");
 
+#if 0
        printf("Rdly\np0: ");
        for (size_t i = 0; i < 8; i++) {
                profile2.rdly_p0 = i;
@@ -198,6 +208,7 @@ int main(int argc, char *argv[]) {
         printf("\tp1 rdly: %d\n", profile2.rdly_p1);
 
        gram_reset_burstdet(&ctx);
+#endif
 
        srand(time(NULL));
        for (i = 0; i < kPatternSize; i++) {
@@ -220,6 +231,26 @@ int main(int argc, char *argv[]) {
                printf("done\n");
        }
 
+       printf("Dumping data sequence...\n");
+       for (i = 0; i < kPatternSize; i++) {
+               if ((i % kDumpWidth) == 0) {
+                       printf("%08x | ", ddr_base+4*i);
+               }
+
+               expected_value = pattern[i];
+
+               for (int j = 3; j >= 0; j--) {
+                       printf("%02x", ((uint8_t*)(&expected_value))[j]);
+               }
+
+               if ((i % kDumpWidth) == kDumpWidth-1) {
+                       printf("\n");
+               } else {
+                       printf(" ");
+               }
+       }
+       printf("\n");
+
        printf("Reading data sequence...\n");
        for (i = 0; i < kPatternSize; i++) {
                if ((i % kDumpWidth) == 0) {
@@ -237,7 +268,7 @@ int main(int argc, char *argv[]) {
                                printf("\033[0;32m%02x\033[0m", ((uint8_t*)(&read_value))[j]);
                        }
                }
-               
+
                if ((i % kDumpWidth) == kDumpWidth-1) {
                        printf("\n");
                } else {

diff --git a/gram/phy/dfi.py b/gram/phy/dfi.py
index f5a5eb982253b270eb9140f19701667e7dd385d1..aead7a24e713b72133499a31c5cc097c64e6e75e 100644 (file)
--- a/gram/phy/dfi.py
+++ b/gram/phy/dfi.py
@@ -47,7 +47,7 @@ class Interface:
             p.cas.reset = 1
             p.ras.reset = 1
             p.reset.reset = 1
-            p.cs_n.reset = -1
+            p.cs_n.reset = 1
             p.we.reset = 1
             p.act.reset = 1
 

diff --git a/gram/phy/ecp5ddrphy.py b/gram/phy/ecp5ddrphy.py
index b31e19e9cdb6b8d5c8130dc25586285ecf566934..62b42a56874b58302811bd6b53b609be1dcc4204 100644 (file)
--- a/gram/phy/ecp5ddrphy.py
+++ b/gram/phy/ecp5ddrphy.py
@@ -253,17 +253,37 @@ class ECP5DDRPHY(Peripheral, Elaboratable):
             # dfi.Interface it is "reset"
             dfi2pads = {'rst': 'reset', 'cs': 'cs_n'}
             name = dfi2pads.get(name, name) # remap if exists
-            m.d.comb += [
-                pad.o_clk.eq(ClockSignal("dramsync")),
-                pad.o_fclk.eq(ClockSignal("sync2x")),
-            ]
-            for i in range(len(pad.o0)):
+            if name == "reset":
+                m.d.comb += [
+                    pad.o_clk.eq(ClockSignal("sync")),
+                ]
+            else:
                 m.d.comb += [
-                    pad.o0[i].eq(getattr(dfi.phases[0], name)[i]),
-                    pad.o1[i].eq(getattr(dfi.phases[0], name)[i]),
-                    pad.o2[i].eq(getattr(dfi.phases[1], name)[i]),
-                    pad.o3[i].eq(getattr(dfi.phases[1], name)[i]),
+                    pad.o_clk.eq(ClockSignal("dramsync")),
+                    pad.o_fclk.eq(ClockSignal("sync2x")),
                 ]
+            if name == "reset":
+                for i in range(len(pad.o)):
+                    m.d.comb += [
+                        pad.o[i].eq(getattr(dfi.phases[0], name)[i]),
+                    ]
+            elif name == "cs_n":
+                # cs_n can't be directly connected to cs without being inverted first...
+                for i in range(len(pad.o0)):
+                    m.d.comb += [
+                        pad.o0[i].eq(~getattr(dfi.phases[0], name)[i]),
+                        pad.o1[i].eq(~getattr(dfi.phases[0], name)[i]),
+                        pad.o2[i].eq(~getattr(dfi.phases[1], name)[i]),
+                        pad.o3[i].eq(~getattr(dfi.phases[1], name)[i]),
+                    ]
+            else:
+                for i in range(len(pad.o0)):
+                    m.d.comb += [
+                        pad.o0[i].eq(getattr(dfi.phases[0], name)[i]),
+                        pad.o1[i].eq(getattr(dfi.phases[0], name)[i]),
+                        pad.o2[i].eq(getattr(dfi.phases[1], name)[i]),
+                        pad.o3[i].eq(getattr(dfi.phases[1], name)[i]),
+                    ]
 
         # DQ ---------------------------------------------------------------------------------------
         dq_oe = Signal()

diff --git a/libgram/src/dfii.c b/libgram/src/dfii.c
index 58519bd8ff77f0f7edb030e9bfbfccdd7b6eb226..17e18dada9b4069698df0d060262fb659423c554 100644 (file)
--- a/libgram/src/dfii.c
+++ b/libgram/src/dfii.c
@@ -15,7 +15,7 @@ static void dfii_setcontrol(const struct gramCtx *ctx, uint8_t val) {
 
 void dfii_setsw(const struct gramCtx *ctx, bool software_control) {
        if (software_control) {
-               dfii_setcontrol(ctx, DFII_CONTROL_CKE|DFII_CONTROL_ODT);
+               dfii_setcontrol(ctx, DFII_CONTROL_CKE|DFII_CONTROL_ODT|DFII_CONTROL_RESET|DFII_COMMAND_CS);
        } else {
                dfii_setcontrol(ctx, DFII_CONTROL_SEL|DFII_CONTROL_RESET);
        }
@@ -59,13 +59,13 @@ void dfii_initseq(const struct gramCtx *ctx, const struct gramProfile *profile)
        /* Release reset */
        dfii_set_p0_address(ctx, 0x0);
        dfii_set_p0_baddress(ctx, 0);
-       dfii_setcontrol(ctx, DFII_CONTROL_ODT);
+       dfii_setcontrol(ctx, DFII_CONTROL_ODT|DFII_CONTROL_RESET);
        cdelay(50000);
 
        /* Bring CKE high */
        dfii_set_p0_address(ctx, 0x0);
        dfii_set_p0_baddress(ctx, 0);
-       dfii_setcontrol(ctx, DFII_CONTROL_CKE|DFII_CONTROL_ODT);
+       dfii_setcontrol(ctx, DFII_CONTROL_CKE|DFII_CONTROL_ODT|DFII_CONTROL_RESET);
        cdelay(10000);
 
        /* Load Mode Register 2, CWL=5 */