add a debug verilog dump of one of the FakePHY SocTest cases

to see what is going on

diff --git a/gram/test/test_soc.py b/gram/test/test_soc.py
index ceb8f664d01fa349e8b83c62cc95ddb07ef28dc2..8187b3fcd44c200d20d60ad17626e2f2d5b95219 100644 (file)
--- a/gram/test/test_soc.py
+++ b/gram/test/test_soc.py
@@ -7,6 +7,7 @@ from nmigen import *
 from nmigen.asserts import Assert, Assume
 from nmigen_soc import wishbone, memory
 from nmigen.lib.cdc import ResetSynchronizer
+from nmigen.cli import verilog
 
 from lambdasoc.periph import Peripheral
 from lambdasoc.soc.base import SoC
@@ -141,6 +142,10 @@ class SocTestCase(FHDLTestCase):
             dramcore_addr=0x00000000,
             ddr_addr=0x10000000)
 
+        vl = verilog.convert(soc, ports=None)
+        with open("test_soc_multiple_reads.v", "w") as f:
+            f.write(vl)
+
         def process():
             yield from SocTestCase.init_seq(soc.bus)