add features option to gramCore and PHY wishbone buses, not sure if

this is a good idea or not

diff --git a/gram/core/__init__.py b/gram/core/__init__.py
index 371f674e972342d4a04c86afbeb58c4c9e7fa9d1..14462be1471b1d5783f2208780cdb9bddddf2f0a 100644 (file)
--- a/gram/core/__init__.py
+++ b/gram/core/__init__.py
@@ -10,7 +10,8 @@ from gram.core.crossbar import gramCrossbar
 __ALL__ = ["gramCore"]
 
 class gramCore(Peripheral, Elaboratable):
-    def __init__(self, phy, geom_settings, timing_settings, clk_freq, **kwargs):
+    def __init__(self, phy, geom_settings, timing_settings, clk_freq,
+                       features=frozenset(), **kwargs):
         super().__init__("core")
 
         bank = self.csr_bank()
@@ -41,7 +42,8 @@ class gramCore(Peripheral, Elaboratable):
 
         self.crossbar = gramCrossbar(self.controller.interface)
 
-        self._bridge = self.bridge(data_width=32, granularity=8, alignment=2)
+        self._bridge = self.bridge(data_width=32, granularity=8, alignment=2,
+                                   features=features)
         self.bus = self._bridge.bus
 
     def elaborate(self, platform):

diff --git a/gram/phy/ecp5ddrphy.py b/gram/phy/ecp5ddrphy.py
index e1d1147601001c19afd2c72a3c457ce92c4a0c2d..e3e7f5ff7d8d528ae4113a8f0935206ce12edda3 100644 (file)
--- a/gram/phy/ecp5ddrphy.py
+++ b/gram/phy/ecp5ddrphy.py
@@ -133,7 +133,7 @@ class _DQSBUFMSettingManager(Elaboratable):
 
 
 class ECP5DDRPHY(Peripheral, Elaboratable):
-    def __init__(self, pads, sys_clk_freq=100e6):
+    def __init__(self, pads, features=frozenset(), sys_clk_freq=100e6):
         super().__init__(name="phy")
 
         self.pads = pads
@@ -154,7 +154,8 @@ class ECP5DDRPHY(Peripheral, Elaboratable):
         self.rdly += [bank.csr(3, "rw", name="rdly_p1")]
         self.bitslip = bank.csr(3, "rw") # phase-delay on read
 
-        self._bridge = self.bridge(data_width=32, granularity=8, alignment=2)
+        self._bridge = self.bridge(data_width=32, granularity=8, alignment=2,
+                                   features=features)
         self.bus = self._bridge.bus
 
         addressbits = len(self.pads.a.o0)
@@ -241,7 +242,6 @@ class ECP5DDRPHY(Peripheral, Elaboratable):
         drs = ResetSignal("dramsync")
         m.d.comb += rst.eq(drs)
         #if hasattr(self.pads, "rst"):
-            
 
         # Addresses and Commands ---------------------------------------------------------------
         m.d.comb += [