examples/headless-ecpix5.py

   1 # This file is Copyright (c) 2020 LambdaConcept <contact@lambdaconcept.com>
   2
   3 from nmigen import *
   4 from nmigen.lib.cdc import ResetSynchronizer
   5 from nmigen_soc import wishbone, memory
   6
   7 from lambdasoc.periph.intc import GenericInterruptController
   8 from lambdasoc.periph.serial import AsyncSerialPeripheral
   9 from lambdasoc.periph.sram import SRAMPeripheral
  10 from lambdasoc.periph.timer import TimerPeripheral
  11 from lambdasoc.periph import Peripheral
  12 from lambdasoc.soc.base import SoC
  13
  14 from gram.core import gramCore
  15 from gram.phy.ecp5ddrphy import ECP5DDRPHY
  16 from gram.modules import MT41K256M16
  17 from gram.frontend.wishbone import gramWishbone
  18
  19 from nmigen_boards.ecpix5 import *
  20 from uartbridge import UARTBridge
  21 from crg import *
  22
  23 class DDR3SoC(SoC, Elaboratable):
  24     def __init__(self, *,
  25                  ddrphy_addr, dramcore_addr,
  26                  ddr_addr):
  27         self._decoder = wishbone.Decoder(addr_width=30, data_width=32, granularity=8,
  28                                          features={"cti", "bte"})
  29
  30         self.crg = ECPIX5CRG()
  31
  32         self.ub = UARTBridge(divisor=868, pins=platform.request("uart", 0))
  33
  34         ddr_pins = platform.request("ddr3", 0, dir={"dq":"-", "dqs":"-"},
  35             xdr={"clk":4, "a":4, "ba":4, "clk_en":4, "odt":4, "ras":4, "cas":4, "we":4})
  36         self.ddrphy = DomainRenamer("dramsync")(ECP5DDRPHY(ddr_pins))
  37         self._decoder.add(self.ddrphy.bus, addr=ddrphy_addr)
  38
  39         ddrmodule = MT41K256M16(platform.default_clk_frequency, "1:2")
  40
  41         self.dramcore = DomainRenamer("dramsync")(gramCore(
  42             phy=self.ddrphy,
  43             geom_settings=ddrmodule.geom_settings,
  44             timing_settings=ddrmodule.timing_settings,
  45             clk_freq=platform.default_clk_frequency))
  46         self._decoder.add(self.dramcore.bus, addr=dramcore_addr)
  47
  48         self.drambone = DomainRenamer("dramsync")(gramWishbone(self.dramcore))
  49         self._decoder.add(self.drambone.bus, addr=ddr_addr)
  50
  51         self.memory_map = self._decoder.bus.memory_map
  52
  53         self.clk_freq = platform.default_clk_frequency
  54
  55     def elaborate(self, platform):
  56         m = Module()
  57
  58         m.submodules.sysclk = self.crg
  59
  60         m.submodules.ub = self.ub
  61
  62         m.submodules.decoder = self._decoder
  63         m.submodules.ddrphy = self.ddrphy
  64         m.submodules.dramcore = self.dramcore
  65         m.submodules.drambone = self.drambone
  66
  67         m.d.comb += [
  68             self.ub.bus.connect(self._decoder.bus),
  69         ]
  70
  71         return m
  72
  73
  74 if __name__ == "__main__":
  75     platform = ECPIX585Platform()
  76
  77     soc = DDR3SoC(ddrphy_addr=0x00008000, dramcore_addr=0x00009000,
  78         ddr_addr=0x10000000)
  79
  80     soc.build(do_build=True)
  81     platform.build(soc, do_program=True)