examples/headless-versa-85.py

   1 # This file is Copyright (c) 2020 LambdaConcept <contact@lambdaconcept.com>
   2 # This file is Copyright (c) 2022 Raptor Engineering, LLC <support@raptorengineering.com>
   3
   4 from nmigen import *
   5 from nmigen.lib.cdc import ResetSynchronizer
   6 from nmigen_soc import wishbone, memory
   7
   8 from lambdasoc.cpu.minerva import MinervaCPU
   9 from lambdasoc.periph.intc import GenericInterruptController
  10 from lambdasoc.periph.serial import AsyncSerialPeripheral
  11 from lambdasoc.periph.sram import SRAMPeripheral
  12 from lambdasoc.periph.timer import TimerPeripheral
  13 from lambdasoc.periph import Peripheral
  14 from lambdasoc.soc.base import SoC
  15
  16 from gram.core import gramCore
  17 from gram.phy.ecp5ddrphy import ECP5DDRPHY
  18 from gram.modules import MT41K64M16
  19 from gram.frontend.wishbone import gramWishbone
  20
  21 from nmigen_boards.versa_ecp5 import VersaECP5Platform85
  22 from ecp5_crg import ECP5CRG
  23 #from crg import ECPIX5CRG
  24 from uartbridge import UARTBridge
  25 from crg import *
  26
  27 class DDR3SoC(SoC, Elaboratable):
  28     def __init__(self, *,
  29                  ddrphy_addr, dramcore_addr,
  30                  ddr_addr):
  31         self._decoder = wishbone.Decoder(addr_width=30, data_width=32, granularity=8,
  32                                          features={"cti", "bte"})
  33
  34         #desired_sys_clk_freq = 100e6
  35         #desired_sys_clk_freq = 90e6
  36         #desired_sys_clk_freq = 75e6
  37         #desired_sys_clk_freq = 70e6
  38         #desired_sys_clk_freq = 65e6
  39         #desired_sys_clk_freq = 60e6
  40         #desired_sys_clk_freq = 55e6
  41         desired_sys_clk_freq = 50e6
  42
  43         #self.crg = ECPIX5CRG()
  44         self.crg = ECP5CRG(sys_clk_freq=desired_sys_clk_freq)
  45
  46         self.ub = UARTBridge(divisor=int(desired_sys_clk_freq/115200), pins=platform.request("uart", 0))
  47
  48         ddr_pins = platform.request("ddr3", 0, dir={"dq":"-", "dqs":"-"},
  49             xdr={"clk":4, "a":4, "ba":4, "clk_en":4, "odt":4, "ras":4, "cas":4, "we":4, "cs":4, "rst":1})
  50         self.ddrphy = DomainRenamer("dramsync")(ECP5DDRPHY(ddr_pins))
  51         self._decoder.add(self.ddrphy.bus, addr=ddrphy_addr)
  52
  53         ddrmodule = MT41K64M16(self.crg.sys_clk_freq, "1:2")
  54
  55         self.dramcore = DomainRenamer("dramsync")(gramCore(
  56             phy=self.ddrphy,
  57             geom_settings=ddrmodule.geom_settings,
  58             timing_settings=ddrmodule.timing_settings,
  59             clk_freq=self.crg.sys_clk_freq))
  60         self._decoder.add(self.dramcore.bus, addr=dramcore_addr)
  61
  62         self.drambone = DomainRenamer("dramsync")(gramWishbone(self.dramcore))
  63         self._decoder.add(self.drambone.bus, addr=ddr_addr)
  64
  65         self.memory_map = self._decoder.bus.memory_map
  66
  67         self.clk_freq = self.crg.sys_clk_freq
  68
  69     def elaborate(self, platform):
  70         m = Module()
  71
  72         m.submodules.sysclk = self.crg
  73
  74         m.submodules.ub = self.ub
  75
  76         m.submodules.decoder = self._decoder
  77         m.submodules.ddrphy = self.ddrphy
  78         m.submodules.dramcore = self.dramcore
  79         m.submodules.drambone = self.drambone
  80
  81         m.d.comb += [
  82             self.ub.bus.connect(self._decoder.bus),
  83         ]
  84
  85         return m
  86
  87
  88 if __name__ == "__main__":
  89     platform = VersaECP5Platform85()
  90
  91     soc = DDR3SoC(ddrphy_addr=0x00008000, dramcore_addr=0x00009000,
  92         ddr_addr=0x10000000)
  93
  94     soc.build(do_build=True)
  95     platform.build(soc, do_program=True)