examples/headless-versa-85.py

   1 # This file is Copyright (c) 2020 LambdaConcept <contact@lambdaconcept.com>
   2 # This file is Copyright (c) 2022 Raptor Engineering, LLC <support@raptorengineering.com>
   3
   4 from nmigen import *
   5 from nmigen.lib.cdc import ResetSynchronizer
   6 from nmigen_soc import wishbone, memory
   7
   8 from lambdasoc.periph.intc import GenericInterruptController
   9 from lambdasoc.periph.serial import AsyncSerialPeripheral
  10 from lambdasoc.periph.sram import SRAMPeripheral
  11 from lambdasoc.periph.timer import TimerPeripheral
  12 from lambdasoc.periph import Peripheral
  13 from lambdasoc.soc.base import SoC
  14
  15 from gram.core import gramCore
  16 from gram.phy.ecp5ddrphy import ECP5DDRPHY
  17 from gram.modules import MT41K64M16
  18 from gram.frontend.wishbone import gramWishbone
  19
  20 from nmigen_boards.versa_ecp5 import VersaECP5Platform85
  21 from ecp5_crg import ECP5CRG
  22 #from crg import ECPIX5CRG
  23 from uartbridge import UARTBridge
  24 from crg import *
  25
  26 class DDR3SoC(SoC, Elaboratable):
  27     def __init__(self, *,
  28                  ddrphy_addr, dramcore_addr,
  29                  ddr_addr):
  30         self._decoder = wishbone.Decoder(addr_width=30, data_width=32, granularity=8,
  31                                          features={"cti", "bte"})
  32
  33         #desired_sys_clk_freq = 100e6
  34         #desired_sys_clk_freq = 90e6
  35         #desired_sys_clk_freq = 75e6
  36         #desired_sys_clk_freq = 70e6
  37         #desired_sys_clk_freq = 65e6
  38         #desired_sys_clk_freq = 60e6
  39         #desired_sys_clk_freq = 55e6
  40         desired_sys_clk_freq = 50e6
  41
  42         #self.crg = ECPIX5CRG()
  43         self.crg = ECP5CRG(sys_clk_freq=desired_sys_clk_freq)
  44
  45         self.ub = UARTBridge(divisor=int(desired_sys_clk_freq/115200), pins=platform.request("uart", 0))
  46
  47         ddr_pins = platform.request("ddr3", 0, dir={"dq":"-", "dqs":"-"},
  48             xdr={"clk":4, "a":4, "ba":4, "clk_en":4, "odt":4, "ras":4, "cas":4, "we":4, "cs":4, "rst":1})
  49         self.ddrphy = DomainRenamer("dramsync")(ECP5DDRPHY(ddr_pins))
  50         self._decoder.add(self.ddrphy.bus, addr=ddrphy_addr)
  51
  52         ddrmodule = MT41K64M16(self.crg.sys_clk_freq, "1:2")
  53
  54         self.dramcore = DomainRenamer("dramsync")(gramCore(
  55             phy=self.ddrphy,
  56             geom_settings=ddrmodule.geom_settings,
  57             timing_settings=ddrmodule.timing_settings,
  58             clk_freq=self.crg.sys_clk_freq))
  59         self._decoder.add(self.dramcore.bus, addr=dramcore_addr)
  60
  61         self.drambone = DomainRenamer("dramsync")(gramWishbone(self.dramcore))
  62         self._decoder.add(self.drambone.bus, addr=ddr_addr)
  63
  64         self.memory_map = self._decoder.bus.memory_map
  65
  66         self.clk_freq = self.crg.sys_clk_freq
  67
  68     def elaborate(self, platform):
  69         m = Module()
  70
  71         m.submodules.sysclk = self.crg
  72
  73         m.submodules.ub = self.ub
  74
  75         m.submodules.decoder = self._decoder
  76         m.submodules.ddrphy = self.ddrphy
  77         m.submodules.dramcore = self.dramcore
  78         m.submodules.drambone = self.drambone
  79
  80         m.d.comb += [
  81             self.ub.bus.connect(self._decoder.bus),
  82         ]
  83
  84         return m
  85
  86
  87 if __name__ == "__main__":
  88     platform = VersaECP5Platform85()
  89
  90     soc = DDR3SoC(ddrphy_addr=0x00008000, dramcore_addr=0x00009000,
  91         ddr_addr=0x10000000)
  92
  93     soc.build(do_build=True)
  94     platform.build(soc, do_program=True)