experiments10_verilog/non_generated/pll.v

   1 (* blackbox = 1 *)
   2 module pll(ref_v, div_out_test, a0, a1, vco_test_ana, out_v);
   3   input a0;
   4   input a1;
   5   output div_out_test;
   6   output out_v;
   7   input ref_v;
   8   output vco_test_ana;
   9 endmodule
  10