add missing reset-HI values to cas_n, cs_n, we_n and act_n
[gram.git] / gram / phy / dfi.py
1 # This file is Copyright (c) 2015 Sebastien Bourdeauducq <sb@m-labs.hk>
2 # This file is Copyright (c) 2020 LambdaConcept <contact@lambdaconcept.com>
3
4 from nmigen import *
5 from nmigen.hdl.rec import *
6
7 __ALL__ = ["Interface"]
8
9
10 def phase_description(addressbits, bankbits, nranks, databits):
11 return [
12 # cmd description
13 ("address", addressbits, DIR_FANOUT),
14 ("bank", bankbits, DIR_FANOUT),
15 ("cas", 1, DIR_FANOUT),
16 ("cs_n", nranks, DIR_FANOUT),
17 ("ras", 1, DIR_FANOUT),
18 ("we", 1, DIR_FANOUT),
19 ("clk_en", nranks, DIR_FANOUT),
20 ("odt", nranks, DIR_FANOUT),
21 ("reset_n", 1, DIR_FANOUT),
22 ("act", 1, DIR_FANOUT),
23 # wrdata description
24 ("wrdata", databits, DIR_FANOUT),
25 ("wrdata_en", 1, DIR_FANOUT),
26 ("wrdata_mask", databits//8, DIR_FANOUT),
27 # rddata description
28 ("rddata_en", 1, DIR_FANOUT),
29 ("rddata", databits, DIR_FANIN),
30 ("rddata_valid", 1, DIR_FANIN),
31 ]
32
33
34 class Interface:
35 def __init__(self, addressbits, bankbits, nranks, databits, nphases=1,
36 name=None):
37 print ("DFI Interface", name, "addr", addressbits,
38 "bankbits", bankbits, "nranks", nranks, "data", databits,
39 "phases", nphases)
40 self.phases = []
41 for p in range(nphases):
42 p = Record(phase_description(addressbits, bankbits,
43 nranks, databits),
44 name=name)
45 self.phases += [p]
46 # set all logic-inverted x_n signal resets to on at power-up
47 p.cas.reset = 1
48 p.cs_n.reset = -1
49 p.we.reset = 1
50 p.act.reset = 1
51
52 def connect(self, target):
53 if not isinstance(target, Interface):
54 raise TypeError("Target must be an instance of Interface, not {!r}"
55 .format(target))
56
57 ret = []
58 for i in range(min(len(self.phases), len(target.phases))):
59 ret += [self.phases[i].connect(target.phases[i])]
60
61 return ret