gram/phy/ecp5ddrphy.py

   1 # This file is Copyright (c) 2019 David Shah <dave@ds0.me>
   2 # This file is Copyright (c) 2019-2020 Florent Kermarrec <florent@enjoy-digital.fr>
   3 # This file is Copyright (c) 2020 LambdaConcept <contact@lambdaconcept.com>
   4 # License: BSD
   5
   6 # 1:2 frequency-ratio DDR3 PHY for Lattice's ECP5
   7 # DDR3: 800 MT/s
   8
   9 import math
  10
  11 from nmigen import *
  12 from nmigen.lib.cdc import FFSynchronizer
  13 from nmigen.utils import log2_int
  14
  15 from lambdasoc.periph import Peripheral
  16
  17 import gram.stream as stream
  18 from gram.common import *
  19 from gram.phy.dfi import Interface
  20 from gram.compat import Timeline
  21
  22 __all__ = ["ECP5DDRPHY"]
  23
  24
  25 class ECP5DDRPHYInit(Elaboratable):
  26     def __init__(self):
  27         self.pause = Signal()
  28         self.stop = Signal()
  29         self.delay = Signal()
  30         self.reset = Signal()
  31
  32     def elaborate(self, platform):
  33         m = Module()
  34
  35         new_lock = Signal()
  36         update = Signal()
  37         freeze = Signal()
  38
  39         # DDRDLLA instance -------------------------------------------------------------------------
  40         _lock = Signal()
  41         delay = Signal()
  42         m.submodules += Instance("DDRDLLA",
  43             i_CLK=ClockSignal("sync2x"),
  44             i_RST=ResetSignal("init"),
  45             i_UDDCNTLN=~update,
  46             i_FREEZE=freeze,
  47             o_DDRDEL=delay,
  48             o_LOCK=_lock)
  49         lock = Signal()
  50         lock_d = Signal()
  51         m.submodules += FFSynchronizer(_lock, lock, o_domain="init")
  52         m.d.init += lock_d.eq(lock)
  53         m.d.sync += new_lock.eq(lock & ~lock_d)
  54
  55         # DDRDLLA/DDQBUFM/ECLK initialization sequence ---------------------------------------------
  56         t = 8  # in cycles
  57         tl = Timeline([
  58             (1*t,  [freeze.eq(1)]),  # Freeze DDRDLLA
  59             (2*t,  [self.stop.eq(1)]),   # Stop ECLK domain
  60             (3*t,  [self.reset.eq(1)]),  # Reset ECLK domain
  61             (4*t,  [self.reset.eq(0)]),  # Release ECLK domain reset
  62             (5*t,  [self.stop.eq(0)]),   # Release ECLK domain stop
  63             (6*t,  [freeze.eq(0)]),  # Release DDRDLLA freeze
  64             (7*t,  [self.pause.eq(1)]),  # Pause DQSBUFM
  65             (8*t,  [update.eq(1)]),  # Update DDRDLLA
  66             (9*t,  [update.eq(0)]),  # Release DDRDMMA update
  67             (10*t, [self.pause.eq(0)]),  # Release DQSBUFM pause
  68         ])
  69         m.submodules += tl
  70         # Wait DDRDLLA Lock
  71         m.d.comb += tl.trigger.eq(new_lock)
  72
  73         m.d.comb += self.delay.eq(delay)
  74
  75         return m
  76
  77
  78 class _DQSBUFMSettingManager(Elaboratable):
  79     """DQSBUFM setting manager.
  80
  81     The DQSBUFM primitive requires a very basic sequence when updating
  82     read delay or other parameters. This elaboratable generates this
  83     sequence from CSR events.
  84
  85     Parameters
  86     ----------
  87     rdly_slr : CSR
  88         CSR storing the rdly value.
  89
  90     Attributes
  91     ----------
  92     pause : Signal(), out
  93         Pause signal for DQSBUFM.
  94     readclksel : Signal(3), out
  95         Readclksel signal for DQSBUFM.
  96     """
  97     def __init__(self, rdly_csr):
  98         self.rdly_csr = rdly_csr
  99
 100         self.pause = Signal()
 101         self.readclksel = Signal(3)
 102
 103     def elaborate(self, platform):
 104         m = Module()
 105
 106         with m.FSM():
 107             with m.State("Idle"):
 108                 with m.If(self.rdly_csr.w_stb):
 109                     m.d.sync += self.pause.eq(1)
 110                     m.next = "RdlyUpdateRequested"
 111
 112             with m.State("RdlyUpdateRequested"):
 113                 m.d.sync += self.readclksel.eq(self.rdly_csr.w_data)
 114                 m.next = "ResetPause"
 115
 116             with m.State("ResetPause"):
 117                 m.d.sync += self.pause.eq(0)
 118                 m.next = "Idle"
 119
 120         return m
 121
 122
 123 class ECP5DDRPHY(Peripheral, Elaboratable):
 124     def __init__(self, pads, sys_clk_freq=100e6):
 125         super().__init__(name="phy")
 126
 127         self.pads = pads
 128         self._sys_clk_freq = sys_clk_freq
 129
 130         databits = len(self.pads.dq.io)
 131         if databits % 8 != 0:
 132             raise ValueError("DQ pads should come in a multiple of 8")
 133
 134         # CSR
 135         bank = self.csr_bank()
 136
 137         self.burstdet = bank.csr(databits//8, "rw")
 138
 139         self.rdly = []
 140         self.rdly += [bank.csr(3, "rw", name="rdly_p0")]
 141         self.rdly += [bank.csr(3, "rw", name="rdly_p1")]
 142
 143         self._bridge = self.bridge(data_width=32, granularity=8, alignment=2)
 144         self.bus = self._bridge.bus
 145
 146         addressbits = len(self.pads.a.o0)
 147         bankbits = len(self.pads.ba.o0)
 148         nranks = 1 if not hasattr(self.pads, "cs") else len(self.pads.cs.o0)
 149         databits = len(self.pads.dq.io)
 150         self.dfi = Interface(addressbits, bankbits, nranks, 4*databits, 4)
 151
 152         # PHY settings -----------------------------------------------------------------------------
 153         tck = 1/(2*self._sys_clk_freq)
 154         nphases = 2
 155         databits = len(self.pads.dq.io)
 156         nranks = 1 if not hasattr(self.pads, "cs") else len(self.pads.cs.o0)
 157         cl, cwl = get_cl_cw("DDR3", tck)
 158         cl_sys_latency = get_sys_latency(nphases, cl)
 159         cwl_sys_latency = get_sys_latency(nphases, cwl)
 160         rdcmdphase, rdphase = get_sys_phases(nphases, cl_sys_latency, cl)
 161         wrcmdphase, wrphase = get_sys_phases(nphases, cwl_sys_latency, cwl)
 162         self.settings = PhySettings(
 163             phytype="ECP5DDRPHY",
 164             memtype="DDR3",
 165             databits=databits,
 166             dfi_databits=4*databits,
 167             nranks=nranks,
 168             nphases=nphases,
 169             rdphase=rdphase,
 170             wrphase=wrphase,
 171             rdcmdphase=rdcmdphase,
 172             wrcmdphase=wrcmdphase,
 173             cl=cl,
 174             cwl=cwl,
 175             read_latency=2 + cl_sys_latency + 2 + log2_int(4//nphases) + 4,
 176             write_latency=cwl_sys_latency
 177         )
 178
 179     def elaborate(self, platform):
 180         m = Module()
 181
 182         m.submodules.bridge = self._bridge
 183
 184         tck = 1/(2*self._sys_clk_freq)
 185         nphases = 2
 186         databits = len(self.pads.dq.io)
 187
 188         burstdet_reg = Signal(databits//8, reset_less=True)
 189         m.d.comb += self.burstdet.r_data.eq(burstdet_reg)
 190
 191         # Burstdet clear
 192         with m.If(self.burstdet.w_stb):
 193             m.d.sync += burstdet_reg.eq(0)
 194
 195         # Init -------------------------------------------------------------------------------------
 196         m.submodules.init = init = ECP5DDRPHYInit()
 197
 198         # Parameters -------------------------------------------------------------------------------
 199         cl, cwl = get_cl_cw("DDR3", tck)
 200         cl_sys_latency = get_sys_latency(nphases, cl)
 201         cwl_sys_latency = get_sys_latency(nphases, cwl)
 202
 203         # DFI Interface ----------------------------------------------------------------------------
 204         dfi = self.dfi
 205
 206         bl8_chunk = Signal()
 207
 208         # Clock --------------------------------------------------------------------------------
 209         m.d.comb += [
 210             self.pads.clk.o_clk.eq(ClockSignal("dramsync")),
 211             self.pads.clk.o_fclk.eq(ClockSignal("sync2x")),
 212         ]
 213         for i in range(len(self.pads.clk.o0)):
 214             m.d.comb += [
 215                 self.pads.clk.o0[i].eq(0),
 216                 self.pads.clk.o1[i].eq(1),
 217                 self.pads.clk.o2[i].eq(0),
 218                 self.pads.clk.o3[i].eq(1),
 219             ]
 220
 221         # Addresses and Commands ---------------------------------------------------------------
 222         m.d.comb += [
 223             self.pads.a.o_clk.eq(ClockSignal("dramsync")),
 224             self.pads.a.o_fclk.eq(ClockSignal("sync2x")),
 225             self.pads.ba.o_clk.eq(ClockSignal("dramsync")),
 226             self.pads.ba.o_fclk.eq(ClockSignal("sync2x")),
 227         ]
 228         for i in range(len(self.pads.a.o0)):
 229             m.d.comb += [
 230                 self.pads.a.o0[i].eq(dfi.phases[0].address[i]),
 231                 self.pads.a.o1[i].eq(dfi.phases[0].address[i]),
 232                 self.pads.a.o2[i].eq(dfi.phases[1].address[i]),
 233                 self.pads.a.o3[i].eq(dfi.phases[1].address[i]),
 234             ]
 235         for i in range(len(self.pads.ba.o0)):
 236             m.d.comb += [
 237                 self.pads.ba.o0[i].eq(dfi.phases[0].bank[i]),
 238                 self.pads.ba.o1[i].eq(dfi.phases[0].bank[i]),
 239                 self.pads.ba.o2[i].eq(dfi.phases[1].bank[i]),
 240                 self.pads.ba.o3[i].eq(dfi.phases[1].bank[i]),
 241             ]
 242
 243         # Control pins
 244         controls = ["ras", "cas", "we", "clk_en", "odt"]
 245         if hasattr(self.pads, "reset"):
 246             controls.append("reset")
 247         if hasattr(self.pads, "cs"):
 248             controls.append("cs")
 249         for name in controls:
 250             m.d.comb += [
 251                 getattr(self.pads, name).o_clk.eq(ClockSignal("dramsync")),
 252                 getattr(self.pads, name).o_fclk.eq(ClockSignal("sync2x")),
 253             ]
 254             for i in range(len(getattr(self.pads, name).o0)):
 255                 m.d.comb += [
 256                     getattr(self.pads, name).o0[i].eq(getattr(dfi.phases[0], name)[i]),
 257                     getattr(self.pads, name).o1[i].eq(getattr(dfi.phases[0], name)[i]),
 258                     getattr(self.pads, name).o2[i].eq(getattr(dfi.phases[1], name)[i]),
 259                     getattr(self.pads, name).o3[i].eq(getattr(dfi.phases[1], name)[i]),
 260                 ]
 261
 262         # DQ ---------------------------------------------------------------------------------------
 263         dq_oe = Signal()
 264         dqs_re = Signal()
 265         dqs_oe = Signal()
 266         dqs_postamble = Signal()
 267         dqs_preamble = Signal()
 268         for i in range(databits//8):
 269             # DQSBUFM
 270             dqs_i = Signal()
 271             dqsr90 = Signal()
 272             dqsw270 = Signal()
 273             dqsw = Signal()
 274             rdpntr = Signal(3)
 275             wrpntr = Signal(3)
 276             burstdet = Signal()
 277             datavalid = Signal()
 278             datavalid_prev = Signal()
 279             m.d.sync += datavalid_prev.eq(datavalid)
 280
 281             dqsbufm_manager = _DQSBUFMSettingManager(self.rdly[i])
 282             setattr(m.submodules, f"dqsbufm_manager{i}", dqsbufm_manager)
 283
 284             m.submodules += Instance("DQSBUFM",
 285                 p_DQS_LI_DEL_ADJ="MINUS",
 286                 p_DQS_LI_DEL_VAL=1,
 287                 p_DQS_LO_DEL_ADJ="MINUS",
 288                 p_DQS_LO_DEL_VAL=4,
 289
 290                 # Delay
 291                 i_DYNDELAY0=0,
 292                 i_DYNDELAY1=0,
 293                 i_DYNDELAY2=0,
 294                 i_DYNDELAY3=0,
 295                 i_DYNDELAY4=0,
 296                 i_DYNDELAY5=0,
 297                 i_DYNDELAY6=0,
 298                 i_DYNDELAY7=0,
 299
 300                 # Clocks / Reset
 301                 i_SCLK=ClockSignal("sync"),
 302                 i_ECLK=ClockSignal("sync2x"),
 303                 i_RST=ResetSignal("dramsync"),
 304                 i_DDRDEL=init.delay,
 305                 i_PAUSE=init.pause | dqsbufm_manager.pause,
 306
 307                 # Control
 308                 # Assert LOADNs to use DDRDEL control
 309                 i_RDLOADN=0,
 310                 i_RDMOVE=0,
 311                 i_RDDIRECTION=1,
 312                 i_WRLOADN=0,
 313                 i_WRMOVE=0,
 314                 i_WRDIRECTION=1,
 315
 316                 # Reads (generate shifted DQS clock for reads)
 317                 i_READ0=dqs_re,
 318                 i_READ1=dqs_re,
 319                 i_READCLKSEL0=dqsbufm_manager.readclksel[0],
 320                 i_READCLKSEL1=dqsbufm_manager.readclksel[1],
 321                 i_READCLKSEL2=dqsbufm_manager.readclksel[2],
 322                 i_DQSI=dqs_i,
 323                 o_DQSR90=dqsr90,
 324                 o_RDPNTR0=rdpntr[0],
 325                 o_RDPNTR1=rdpntr[1],
 326                 o_RDPNTR2=rdpntr[2],
 327                 o_WRPNTR0=wrpntr[0],
 328                 o_WRPNTR1=wrpntr[1],
 329                 o_WRPNTR2=wrpntr[2],
 330                 o_BURSTDET=burstdet,
 331                 o_DATAVALID=datavalid,
 332
 333                 # Writes (generate shifted ECLK clock for writes)
 334                 o_DQSW270=dqsw270,
 335                 o_DQSW=dqsw)
 336
 337             with m.If(burstdet):
 338                 m.d.sync += burstdet_reg[i].eq(1)
 339
 340             # DQS and DM ---------------------------------------------------------------------------
 341             dm_o_data = Signal(8)
 342             dm_o_data_d = Signal(8)
 343             dm_o_data_muxed = Signal(4)
 344             m.d.comb += dm_o_data.eq(Cat(
 345                 dfi.phases[0].wrdata_mask[0*databits//8+i],
 346                 dfi.phases[0].wrdata_mask[1*databits//8+i],
 347                 dfi.phases[0].wrdata_mask[2*databits//8+i],
 348                 dfi.phases[0].wrdata_mask[3*databits//8+i],
 349
 350                 dfi.phases[1].wrdata_mask[0*databits//8+i],
 351                 dfi.phases[1].wrdata_mask[1*databits//8+i],
 352                 dfi.phases[1].wrdata_mask[2*databits//8+i],
 353                 dfi.phases[1].wrdata_mask[3*databits//8+i]),
 354             )
 355             m.d.sync += dm_o_data_d.eq(dm_o_data)
 356
 357             with m.If(bl8_chunk):
 358                 m.d.sync += dm_o_data_muxed.eq(dm_o_data_d[4:])
 359             with m.Else():
 360                 m.d.sync += dm_o_data_muxed.eq(dm_o_data[:4])
 361
 362             m.submodules += Instance("ODDRX2DQA",
 363                 i_RST=ResetSignal("dramsync"),
 364                 i_ECLK=ClockSignal("sync2x"),
 365                 i_SCLK=ClockSignal("dramsync"),
 366                 i_DQSW270=dqsw270,
 367                 i_D0=dm_o_data_muxed[0],
 368                 i_D1=dm_o_data_muxed[1],
 369                 i_D2=dm_o_data_muxed[2],
 370                 i_D3=dm_o_data_muxed[3],
 371                 o_Q=self.pads.dm.o[i])
 372
 373             dqs = Signal()
 374             dqs_oe_n = Signal()
 375             m.submodules += [
 376                 Instance("ODDRX2DQSB",
 377                     i_RST=ResetSignal("dramsync"),
 378                     i_ECLK=ClockSignal("sync2x"),
 379                     i_SCLK=ClockSignal(),
 380                     i_DQSW=dqsw,
 381                     i_D0=0,
 382                     i_D1=1,
 383                     i_D2=0,
 384                     i_D3=1,
 385                     o_Q=dqs),
 386                 Instance("TSHX2DQSA",
 387                     i_RST=ResetSignal("dramsync"),
 388                     i_ECLK=ClockSignal("sync2x"),
 389                     i_SCLK=ClockSignal(),
 390                     i_DQSW=dqsw,
 391                     i_T0=~(dqs_oe | dqs_postamble),
 392                     i_T1=~(dqs_oe | dqs_preamble),
 393                     o_Q=dqs_oe_n),
 394                 Instance("BB",
 395                     i_I=dqs,
 396                     i_T=dqs_oe_n,
 397                     o_O=dqs_i,
 398                     io_B=self.pads.dqs.p[i]),
 399             ]
 400
 401             for j in range(8*i, 8*(i+1)):
 402                 dq_o = Signal()
 403                 dq_i = Signal()
 404                 dq_oe_n = Signal()
 405                 dq_i_delayed = Signal()
 406                 dq_i_data = Signal(4)
 407                 dq_o_data = Signal(8)
 408                 dq_o_data_d = Signal(8)
 409                 dq_o_data_muxed = Signal(4)
 410                 m.d.comb += dq_o_data.eq(Cat(
 411                     dfi.phases[0].wrdata[0*databits+j],
 412                     dfi.phases[0].wrdata[1*databits+j],
 413                     dfi.phases[0].wrdata[2*databits+j],
 414                     dfi.phases[0].wrdata[3*databits+j],
 415                     dfi.phases[1].wrdata[0*databits+j],
 416                     dfi.phases[1].wrdata[1*databits+j],
 417                     dfi.phases[1].wrdata[2*databits+j],
 418                     dfi.phases[1].wrdata[3*databits+j])
 419                 )
 420
 421                 m.d.sync += dq_o_data_d.eq(dq_o_data)
 422                 with m.If(bl8_chunk):
 423                     m.d.sync += dq_o_data_muxed.eq(dq_o_data_d[4:])
 424                 with m.Else():
 425                     m.d.sync += dq_o_data_muxed.eq(dq_o_data[:4])
 426
 427                 m.submodules += [
 428                     Instance("ODDRX2DQA",
 429                         i_RST=ResetSignal("dramsync"),
 430                         i_ECLK=ClockSignal("sync2x"),
 431                         i_SCLK=ClockSignal(),
 432                         i_DQSW270=dqsw270,
 433                         i_D0=dq_o_data_muxed[0],
 434                         i_D1=dq_o_data_muxed[1],
 435                         i_D2=dq_o_data_muxed[2],
 436                         i_D3=dq_o_data_muxed[3],
 437                         o_Q=dq_o),
 438                     Instance("DELAYF",
 439                         p_DEL_MODE="DQS_ALIGNED_X2",
 440                         i_LOADN=1,
 441                         i_MOVE=0,
 442                         i_DIRECTION=0,
 443                         i_A=dq_i,
 444                         o_Z=dq_i_delayed),
 445                     Instance("IDDRX2DQA",
 446                         i_RST=ResetSignal("dramsync"),
 447                         i_ECLK=ClockSignal("sync2x"),
 448                         i_SCLK=ClockSignal(),
 449                         i_DQSR90=dqsr90,
 450                         i_RDPNTR0=rdpntr[0],
 451                         i_RDPNTR1=rdpntr[1],
 452                         i_RDPNTR2=rdpntr[2],
 453                         i_WRPNTR0=wrpntr[0],
 454                         i_WRPNTR1=wrpntr[1],
 455                         i_WRPNTR2=wrpntr[2],
 456                         i_D=dq_i_delayed,
 457                         o_Q0=dq_i_data[0],
 458                         o_Q1=dq_i_data[1],
 459                         o_Q2=dq_i_data[2],
 460                         o_Q3=dq_i_data[3]),
 461                     Instance("TSHX2DQA",
 462                         i_RST=ResetSignal("dramsync"),
 463                         i_ECLK=ClockSignal("sync2x"),
 464                         i_SCLK=ClockSignal(),
 465                         i_DQSW270=dqsw270,
 466                         i_T0=~dq_oe,
 467                         i_T1=~dq_oe,
 468                         o_Q=dq_oe_n),
 469                     Instance("BB",
 470                         i_I=dq_o,
 471                         i_T=dq_oe_n,
 472                         o_O=dq_i,
 473                         io_B=self.pads.dq.io[j])
 474                 ]
 475                 with m.If(~datavalid_prev & datavalid):
 476                     m.d.sync += [
 477                         dfi.phases[0].rddata[0*databits+j].eq(dq_i_data[0]),
 478                         dfi.phases[0].rddata[1*databits+j].eq(dq_i_data[1]),
 479                         dfi.phases[0].rddata[2*databits+j].eq(dq_i_data[2]),
 480                         dfi.phases[0].rddata[3*databits+j].eq(dq_i_data[3]),
 481                     ]
 482                 with m.Elif(datavalid):
 483                     m.d.sync += [
 484                         dfi.phases[1].rddata[0*databits+j].eq(dq_i_data[0]),
 485                         dfi.phases[1].rddata[1*databits+j].eq(dq_i_data[1]),
 486                         dfi.phases[1].rddata[2*databits+j].eq(dq_i_data[2]),
 487                         dfi.phases[1].rddata[3*databits+j].eq(dq_i_data[3]),
 488                     ]
 489
 490         # Read Control Path ------------------------------------------------------------------------
 491         # Creates a shift register of read commands coming from the DFI interface. This shift register
 492         # is used to control DQS read (internal read pulse of the DQSBUF) and to indicate to the
 493         # DFI interface that the read data is valid.
 494         #
 495         # The DQS read must be asserted for 2 sys_clk cycles before the read data is coming back from
 496         # the DRAM (see 6.2.4 READ Pulse Positioning Optimization of FPGA-TN-02035-1.2)
 497         #
 498         # The read data valid is asserted for 1 sys_clk cycle when the data is available on the DFI
 499         # interface, the latency is the sum of the ODDRX2DQA, CAS, IDDRX2DQA latencies.
 500         rddata_en = Signal(self.settings.read_latency)
 501         rddata_en_last = Signal.like(rddata_en)
 502         m.d.comb += rddata_en.eq(Cat(dfi.phases[self.settings.rdphase].rddata_en, rddata_en_last))
 503         m.d.sync += rddata_en_last.eq(rddata_en)
 504         m.d.comb += dqs_re.eq(rddata_en[cl_sys_latency + 0] | rddata_en[cl_sys_latency + 1] | rddata_en[cl_sys_latency + 2])
 505
 506         rddata_valid = Signal()
 507         m.d.sync += rddata_valid.eq(datavalid_prev & ~datavalid)
 508         for phase in dfi.phases:
 509             m.d.comb += phase.rddata_valid.eq(rddata_valid)
 510
 511         # Write Control Path -----------------------------------------------------------------------
 512         # Creates a shift register of write commands coming from the DFI interface. This shift register
 513         # is used to control DQ/DQS tristates and to select write data of the DRAM burst from the DFI
 514         # interface: The PHY is operating in halfrate mode (so provide 4 datas every sys_clk cycles:
 515         # 2x for DDR, 2x for halfrate) but DDR3 requires a burst of 8 datas (BL8) for best efficiency.
 516         # Writes are then performed in 2 sys_clk cycles and data needs to be selected for each cycle.
 517         # FIXME: understand +2
 518         wrdata_en = Signal(cwl_sys_latency + 4)
 519         wrdata_en_last = Signal.like(wrdata_en)
 520         m.d.comb += wrdata_en.eq(Cat(dfi.phases[self.settings.wrphase].wrdata_en, wrdata_en_last))
 521         m.d.sync += wrdata_en_last.eq(wrdata_en)
 522         m.d.comb += dq_oe.eq(wrdata_en[cwl_sys_latency + 1] | wrdata_en[cwl_sys_latency + 2])
 523         m.d.comb += bl8_chunk.eq(wrdata_en[cwl_sys_latency + 1])
 524         m.d.comb += dqs_oe.eq(dq_oe)
 525
 526         # Write DQS Postamble/Preamble Control Path ------------------------------------------------
 527         # Generates DQS Preamble 1 cycle before the first write and Postamble 1 cycle after the last
 528         # write. During writes, DQS tristate is configured as output for at least 4 sys_clk cycles:
 529         # 1 for Preamble, 2 for the Write and 1 for the Postamble.
 530         m.d.comb += dqs_preamble.eq(wrdata_en[cwl_sys_latency + 0] & ~wrdata_en[cwl_sys_latency + 1])
 531         m.d.comb += dqs_postamble.eq(wrdata_en[cwl_sys_latency + 3] & ~wrdata_en[cwl_sys_latency + 2])
 532
 533         return m