gram/phy/ecp5ddrphy.py

   1 # This file is Copyright (c) 2019 David Shah <dave@ds0.me>
   2 # This file is Copyright (c) 2019-2020 Florent Kermarrec <florent@enjoy-digital.fr>
   3 # This file is Copyright (c) 2020 LambdaConcept <contact@lambdaconcept.com>
   4 # License: BSD
   5
   6 # 1:2 frequency-ratio DDR3 PHY for Lattice's ECP5
   7 # DDR3: 800 MT/s
   8
   9 import math
  10
  11 from nmigen import *
  12 from nmigen.hdl.ast import Rose
  13 from nmigen.lib.cdc import FFSynchronizer
  14 from nmigen.utils import log2_int
  15
  16 from lambdasoc.periph import Peripheral
  17
  18 from gram.common import *
  19 from gram.phy.dfi import Interface
  20 from gram.compat import Timeline
  21
  22 __all__ = ["ECP5DDRPHY"]
  23
  24
  25 class ECP5DDRPHYInit(Elaboratable):
  26     def __init__(self):
  27         self.pause = Signal()
  28         self.stop = Signal()
  29         self.delay = Signal()
  30         self.reset = Signal()
  31
  32     def elaborate(self, platform):
  33         m = Module()
  34
  35         update = Signal()
  36         freeze = Signal()
  37
  38         # DDRDLLA instance -------------------------------------------------------------------------
  39         _lock = Signal()
  40         lock = Signal()
  41         lock_d = Signal()
  42         m.submodules += Instance("DDRDLLA",
  43             i_CLK=ClockSignal("sync2x"),
  44             i_RST=ResetSignal("init"),
  45             i_UDDCNTLN=~update,
  46             i_FREEZE=freeze,
  47             o_DDRDEL=self.delay,
  48             o_LOCK=_lock)
  49         m.submodules += FFSynchronizer(_lock, lock, o_domain="init")
  50         m.d.init += lock_d.eq(lock)
  51
  52         # DDRDLLA/DDQBUFM/ECLK initialization sequence ---------------------------------------------
  53         t = 8  # in cycles
  54         tl = Timeline([
  55             (1*t,  [freeze.eq(1)]),  # Freeze DDRDLLA
  56             (2*t,  [self.stop.eq(1)]),   # Stop ECLK domain
  57             (3*t,  [self.reset.eq(1)]),  # Reset ECLK domain
  58             (4*t,  [self.reset.eq(0)]),  # Release ECLK domain reset
  59             (5*t,  [self.stop.eq(0)]),   # Release ECLK domain stop
  60             (6*t,  [freeze.eq(0)]),  # Release DDRDLLA freeze
  61             (7*t,  [self.pause.eq(1)]),  # Pause DQSBUFM
  62             (8*t,  [update.eq(1)]),  # Update DDRDLLA
  63             (9*t,  [update.eq(0)]),  # Release DDRDMMA update
  64             (10*t, [self.pause.eq(0)]),  # Release DQSBUFM pause
  65         ])
  66         m.d.comb += tl.trigger.eq(lock & ~lock_d) # Trigger timeline on lock rising edge
  67         m.submodules += DomainRenamer("init")(tl)
  68
  69         return m
  70
  71
  72 class _DQSBUFMSettingManager(Elaboratable):
  73     """DQSBUFM setting manager.
  74
  75     The DQSBUFM primitive requires a very basic sequence when updating
  76     read delay or other parameters. This elaboratable generates this
  77     sequence from CSR events.
  78
  79     Parameters
  80     ----------
  81     rdly_slr : CSR
  82         CSR storing the rdly value.
  83
  84     Attributes
  85     ----------
  86     pause : Signal(), out
  87         Pause signal for DQSBUFM.
  88     readclksel : Signal(3), out
  89         Readclksel signal for DQSBUFM.
  90     """
  91     def __init__(self, rdly_csr):
  92         self.rdly_csr = rdly_csr
  93
  94         self.pause = Signal()
  95         self.readclksel = Signal(3)
  96
  97     def elaborate(self, platform):
  98         m = Module()
  99
 100         with m.FSM():
 101             with m.State("Idle"):
 102                 with m.If(self.rdly_csr.w_stb):
 103                     m.d.sync += self.pause.eq(1)
 104                     m.next = "RdlyUpdateRequested"
 105
 106             with m.State("RdlyUpdateRequested"):
 107                 m.d.sync += self.readclksel.eq(self.rdly_csr.w_data)
 108                 m.next = "ResetPause"
 109
 110             with m.State("ResetPause"):
 111                 m.d.sync += self.pause.eq(0)
 112                 m.next = "Idle"
 113
 114         return m
 115
 116
 117 class ECP5DDRPHY(Peripheral, Elaboratable):
 118     def __init__(self, pads, sys_clk_freq=100e6):
 119         super().__init__(name="phy")
 120
 121         self.pads = pads
 122         self._sys_clk_freq = sys_clk_freq
 123
 124         databits = len(self.pads.dq.io)
 125         if databits % 8 != 0:
 126             raise ValueError("DQ pads should come in a multiple of 8")
 127
 128         # CSR
 129         bank = self.csr_bank()
 130
 131         self.burstdet = bank.csr(databits//8, "rw")
 132
 133         self.rdly = []
 134         self.rdly += [bank.csr(3, "rw", name="rdly_p0")]
 135         self.rdly += [bank.csr(3, "rw", name="rdly_p1")]
 136
 137         self._bridge = self.bridge(data_width=32, granularity=8, alignment=2)
 138         self.bus = self._bridge.bus
 139
 140         addressbits = len(self.pads.a.o0)
 141         bankbits = len(self.pads.ba.o0)
 142         nranks = 1 if not hasattr(self.pads, "cs") else len(self.pads.cs.o0)
 143         databits = len(self.pads.dq.io)
 144         self.dfi = Interface(addressbits, bankbits, nranks, 4*databits, 4)
 145
 146         # PHY settings -----------------------------------------------------------------------------
 147         tck = 1/(2*self._sys_clk_freq)
 148         nphases = 2
 149         databits = len(self.pads.dq.io)
 150         nranks = 1 if not hasattr(self.pads, "cs") else len(self.pads.cs.o0)
 151         cl, cwl = get_cl_cw("DDR3", tck)
 152         cl_sys_latency = get_sys_latency(nphases, cl)
 153         cwl_sys_latency = get_sys_latency(nphases, cwl)
 154         rdcmdphase, rdphase = get_sys_phases(nphases, cl_sys_latency, cl)
 155         wrcmdphase, wrphase = get_sys_phases(nphases, cwl_sys_latency, cwl)
 156         self.settings = PhySettings(
 157             phytype="ECP5DDRPHY",
 158             memtype="DDR3",
 159             databits=databits,
 160             dfi_databits=4*databits,
 161             nranks=nranks,
 162             nphases=nphases,
 163             rdphase=rdphase,
 164             wrphase=wrphase,
 165             rdcmdphase=rdcmdphase,
 166             wrcmdphase=wrcmdphase,
 167             cl=cl,
 168             cwl=cwl,
 169             read_latency=2 + cl_sys_latency + 2 + log2_int(4//nphases) + 4,
 170             write_latency=cwl_sys_latency
 171         )
 172
 173     def elaborate(self, platform):
 174         m = Module()
 175
 176         m.submodules.bridge = self._bridge
 177
 178         tck = 1/(2*self._sys_clk_freq)
 179         nphases = 2
 180         databits = len(self.pads.dq.io)
 181
 182         burstdet_reg = Signal(databits//8, reset_less=True)
 183         m.d.comb += self.burstdet.r_data.eq(burstdet_reg)
 184
 185         # Burstdet clear
 186         with m.If(self.burstdet.w_stb):
 187             m.d.sync += burstdet_reg.eq(0)
 188
 189         # Init -------------------------------------------------------------------------------------
 190         m.submodules.init = init = ECP5DDRPHYInit()
 191
 192         # Parameters -------------------------------------------------------------------------------
 193         cl, cwl = get_cl_cw("DDR3", tck)
 194         cl_sys_latency = get_sys_latency(nphases, cl)
 195         cwl_sys_latency = get_sys_latency(nphases, cwl)
 196
 197         # DFI Interface ----------------------------------------------------------------------------
 198         dfi = self.dfi
 199
 200         bl8_chunk = Signal()
 201
 202         # Clock --------------------------------------------------------------------------------
 203         m.d.comb += [
 204             self.pads.clk.o_clk.eq(ClockSignal("dramsync")),
 205             self.pads.clk.o_fclk.eq(ClockSignal("sync2x")),
 206         ]
 207         for i in range(len(self.pads.clk.o0)):
 208             m.d.comb += [
 209                 self.pads.clk.o0[i].eq(0),
 210                 self.pads.clk.o1[i].eq(1),
 211                 self.pads.clk.o2[i].eq(0),
 212                 self.pads.clk.o3[i].eq(1),
 213             ]
 214
 215         # Addresses and Commands ---------------------------------------------------------------
 216         m.d.comb += [
 217             self.pads.a.o_clk.eq(ClockSignal("dramsync")),
 218             self.pads.a.o_fclk.eq(ClockSignal("sync2x")),
 219             self.pads.ba.o_clk.eq(ClockSignal("dramsync")),
 220             self.pads.ba.o_fclk.eq(ClockSignal("sync2x")),
 221         ]
 222         for i in range(len(self.pads.a.o0)):
 223             m.d.comb += [
 224                 self.pads.a.o0[i].eq(dfi.phases[0].address[i]),
 225                 self.pads.a.o1[i].eq(dfi.phases[0].address[i]),
 226                 self.pads.a.o2[i].eq(dfi.phases[1].address[i]),
 227                 self.pads.a.o3[i].eq(dfi.phases[1].address[i]),
 228             ]
 229         for i in range(len(self.pads.ba.o0)):
 230             m.d.comb += [
 231                 self.pads.ba.o0[i].eq(dfi.phases[0].bank[i]),
 232                 self.pads.ba.o1[i].eq(dfi.phases[0].bank[i]),
 233                 self.pads.ba.o2[i].eq(dfi.phases[1].bank[i]),
 234                 self.pads.ba.o3[i].eq(dfi.phases[1].bank[i]),
 235             ]
 236
 237         # Control pins
 238         controls = ["ras", "cas", "we", "clk_en", "odt"]
 239         if hasattr(self.pads, "reset"):
 240             controls.append("reset")
 241         if hasattr(self.pads, "cs"):
 242             controls.append("cs")
 243         for name in controls:
 244             m.d.comb += [
 245                 getattr(self.pads, name).o_clk.eq(ClockSignal("dramsync")),
 246                 getattr(self.pads, name).o_fclk.eq(ClockSignal("sync2x")),
 247             ]
 248             for i in range(len(getattr(self.pads, name).o0)):
 249                 m.d.comb += [
 250                     getattr(self.pads, name).o0[i].eq(getattr(dfi.phases[0], name)[i]),
 251                     getattr(self.pads, name).o1[i].eq(getattr(dfi.phases[0], name)[i]),
 252                     getattr(self.pads, name).o2[i].eq(getattr(dfi.phases[1], name)[i]),
 253                     getattr(self.pads, name).o3[i].eq(getattr(dfi.phases[1], name)[i]),
 254                 ]
 255
 256         # DQ ---------------------------------------------------------------------------------------
 257         dq_oe = Signal()
 258         dqs_re = Signal()
 259         dqs_oe = Signal()
 260         dqs_postamble = Signal()
 261         dqs_preamble = Signal()
 262         for i in range(databits//8):
 263             # DQSBUFM
 264             dqs_i = Signal()
 265             dqsr90 = Signal()
 266             dqsw270 = Signal()
 267             dqsw = Signal()
 268             rdpntr = Signal(3)
 269             wrpntr = Signal(3)
 270             burstdet = Signal()
 271             datavalid = Signal()
 272             datavalid_prev = Signal()
 273             m.d.sync += datavalid_prev.eq(datavalid)
 274
 275             dqsbufm_manager = _DQSBUFMSettingManager(self.rdly[i])
 276             setattr(m.submodules, f"dqsbufm_manager{i}", dqsbufm_manager)
 277
 278             m.submodules += Instance("DQSBUFM",
 279                 p_DQS_LI_DEL_ADJ="MINUS",
 280                 p_DQS_LI_DEL_VAL=1,
 281                 p_DQS_LO_DEL_ADJ="MINUS",
 282                 p_DQS_LO_DEL_VAL=4,
 283
 284                 # Delay
 285                 i_DYNDELAY0=0,
 286                 i_DYNDELAY1=0,
 287                 i_DYNDELAY2=0,
 288                 i_DYNDELAY3=0,
 289                 i_DYNDELAY4=0,
 290                 i_DYNDELAY5=0,
 291                 i_DYNDELAY6=0,
 292                 i_DYNDELAY7=0,
 293
 294                 # Clocks / Reset
 295                 i_SCLK=ClockSignal("sync"),
 296                 i_ECLK=ClockSignal("sync2x"),
 297                 i_RST=ResetSignal("dramsync"),
 298                 i_DDRDEL=init.delay,
 299                 i_PAUSE=init.pause | dqsbufm_manager.pause,
 300
 301                 # Control
 302                 # Assert LOADNs to use DDRDEL control
 303                 i_RDLOADN=0,
 304                 i_RDMOVE=0,
 305                 i_RDDIRECTION=1,
 306                 i_WRLOADN=0,
 307                 i_WRMOVE=0,
 308                 i_WRDIRECTION=1,
 309
 310                 # Reads (generate shifted DQS clock for reads)
 311                 i_READ0=dqs_re,
 312                 i_READ1=dqs_re,
 313                 i_READCLKSEL0=dqsbufm_manager.readclksel[0],
 314                 i_READCLKSEL1=dqsbufm_manager.readclksel[1],
 315                 i_READCLKSEL2=dqsbufm_manager.readclksel[2],
 316                 i_DQSI=dqs_i,
 317                 o_DQSR90=dqsr90,
 318                 o_RDPNTR0=rdpntr[0],
 319                 o_RDPNTR1=rdpntr[1],
 320                 o_RDPNTR2=rdpntr[2],
 321                 o_WRPNTR0=wrpntr[0],
 322                 o_WRPNTR1=wrpntr[1],
 323                 o_WRPNTR2=wrpntr[2],
 324                 o_BURSTDET=burstdet,
 325                 o_DATAVALID=datavalid,
 326
 327                 # Writes (generate shifted ECLK clock for writes)
 328                 o_DQSW270=dqsw270,
 329                 o_DQSW=dqsw)
 330
 331             with m.If(Rose(burstdet)):
 332                 m.d.sync += burstdet_reg[i].eq(1)
 333
 334             # DQS and DM ---------------------------------------------------------------------------
 335             dm_o_data = Signal(8)
 336             dm_o_data_d = Signal(8, reset_less=True)
 337             dm_o_data_muxed = Signal(4, reset_less=True)
 338             m.d.comb += dm_o_data.eq(Cat(
 339                 dfi.phases[0].wrdata_mask[0*databits//8+i],
 340                 dfi.phases[0].wrdata_mask[1*databits//8+i],
 341                 dfi.phases[0].wrdata_mask[2*databits//8+i],
 342                 dfi.phases[0].wrdata_mask[3*databits//8+i],
 343
 344                 dfi.phases[1].wrdata_mask[0*databits//8+i],
 345                 dfi.phases[1].wrdata_mask[1*databits//8+i],
 346                 dfi.phases[1].wrdata_mask[2*databits//8+i],
 347                 dfi.phases[1].wrdata_mask[3*databits//8+i]),
 348             )
 349             m.d.sync += dm_o_data_d.eq(dm_o_data)
 350
 351             with m.If(bl8_chunk):
 352                 m.d.sync += dm_o_data_muxed.eq(dm_o_data_d[4:])
 353             with m.Else():
 354                 m.d.sync += dm_o_data_muxed.eq(dm_o_data[:4])
 355
 356             m.submodules += Instance("ODDRX2DQA",
 357                 i_RST=ResetSignal("dramsync"),
 358                 i_ECLK=ClockSignal("sync2x"),
 359                 i_SCLK=ClockSignal("dramsync"),
 360                 i_DQSW270=dqsw270,
 361                 i_D0=dm_o_data_muxed[0],
 362                 i_D1=dm_o_data_muxed[1],
 363                 i_D2=dm_o_data_muxed[2],
 364                 i_D3=dm_o_data_muxed[3],
 365                 o_Q=self.pads.dm.o[i])
 366
 367             dqs = Signal()
 368             dqs_oe_n = Signal()
 369             m.submodules += [
 370                 Instance("ODDRX2DQSB",
 371                     i_RST=ResetSignal("dramsync"),
 372                     i_ECLK=ClockSignal("sync2x"),
 373                     i_SCLK=ClockSignal(),
 374                     i_DQSW=dqsw,
 375                     i_D0=0,
 376                     i_D1=1,
 377                     i_D2=0,
 378                     i_D3=1,
 379                     o_Q=dqs),
 380                 Instance("TSHX2DQSA",
 381                     i_RST=ResetSignal("dramsync"),
 382                     i_ECLK=ClockSignal("sync2x"),
 383                     i_SCLK=ClockSignal(),
 384                     i_DQSW=dqsw,
 385                     i_T0=~(dqs_oe | dqs_postamble),
 386                     i_T1=~(dqs_oe | dqs_preamble),
 387                     o_Q=dqs_oe_n),
 388                 Instance("BB",
 389                     i_I=dqs,
 390                     i_T=dqs_oe_n,
 391                     o_O=dqs_i,
 392                     io_B=self.pads.dqs.p[i]),
 393             ]
 394
 395             for j in range(8*i, 8*(i+1)):
 396                 dq_o = Signal()
 397                 dq_i = Signal()
 398                 dq_oe_n = Signal()
 399                 dq_i_delayed = Signal()
 400                 dq_i_data = Signal(4)
 401                 dq_o_data = Signal(8)
 402                 dq_o_data_d = Signal(8, reset_less=True)
 403                 dq_o_data_muxed = Signal(4, reset_less=True)
 404                 m.d.comb += dq_o_data.eq(Cat(
 405                     dfi.phases[0].wrdata[0*databits+j],
 406                     dfi.phases[0].wrdata[1*databits+j],
 407                     dfi.phases[0].wrdata[2*databits+j],
 408                     dfi.phases[0].wrdata[3*databits+j],
 409                     dfi.phases[1].wrdata[0*databits+j],
 410                     dfi.phases[1].wrdata[1*databits+j],
 411                     dfi.phases[1].wrdata[2*databits+j],
 412                     dfi.phases[1].wrdata[3*databits+j])
 413                 )
 414
 415                 m.d.sync += dq_o_data_d.eq(dq_o_data)
 416                 with m.If(bl8_chunk):
 417                     m.d.sync += dq_o_data_muxed.eq(dq_o_data_d[4:])
 418                 with m.Else():
 419                     m.d.sync += dq_o_data_muxed.eq(dq_o_data[:4])
 420
 421                 m.submodules += [
 422                     Instance("ODDRX2DQA",
 423                         i_RST=ResetSignal("dramsync"),
 424                         i_ECLK=ClockSignal("sync2x"),
 425                         i_SCLK=ClockSignal(),
 426                         i_DQSW270=dqsw270,
 427                         i_D0=dq_o_data_muxed[0],
 428                         i_D1=dq_o_data_muxed[1],
 429                         i_D2=dq_o_data_muxed[2],
 430                         i_D3=dq_o_data_muxed[3],
 431                         o_Q=dq_o),
 432                     Instance("DELAYF",
 433                         p_DEL_MODE="DQS_ALIGNED_X2",
 434                         i_LOADN=1,
 435                         i_MOVE=0,
 436                         i_DIRECTION=0,
 437                         i_A=dq_i,
 438                         o_Z=dq_i_delayed),
 439                     Instance("IDDRX2DQA",
 440                         i_RST=ResetSignal("dramsync"),
 441                         i_ECLK=ClockSignal("sync2x"),
 442                         i_SCLK=ClockSignal(),
 443                         i_DQSR90=dqsr90,
 444                         i_RDPNTR0=rdpntr[0],
 445                         i_RDPNTR1=rdpntr[1],
 446                         i_RDPNTR2=rdpntr[2],
 447                         i_WRPNTR0=wrpntr[0],
 448                         i_WRPNTR1=wrpntr[1],
 449                         i_WRPNTR2=wrpntr[2],
 450                         i_D=dq_i_delayed,
 451                         o_Q0=dq_i_data[0],
 452                         o_Q1=dq_i_data[1],
 453                         o_Q2=dq_i_data[2],
 454                         o_Q3=dq_i_data[3]),
 455                     Instance("TSHX2DQA",
 456                         i_RST=ResetSignal("dramsync"),
 457                         i_ECLK=ClockSignal("sync2x"),
 458                         i_SCLK=ClockSignal(),
 459                         i_DQSW270=dqsw270,
 460                         i_T0=~dq_oe,
 461                         i_T1=~dq_oe,
 462                         o_Q=dq_oe_n),
 463                     Instance("BB",
 464                         i_I=dq_o,
 465                         i_T=dq_oe_n,
 466                         o_O=dq_i,
 467                         io_B=self.pads.dq.io[j])
 468                 ]
 469                 with m.If(~datavalid_prev & datavalid):
 470                     m.d.sync += [
 471                         dfi.phases[0].rddata[0*databits+j].eq(dq_i_data[0]),
 472                         dfi.phases[0].rddata[1*databits+j].eq(dq_i_data[1]),
 473                         dfi.phases[0].rddata[2*databits+j].eq(dq_i_data[2]),
 474                         dfi.phases[0].rddata[3*databits+j].eq(dq_i_data[3]),
 475                     ]
 476                 with m.Elif(datavalid):
 477                     m.d.sync += [
 478                         dfi.phases[1].rddata[0*databits+j].eq(dq_i_data[0]),
 479                         dfi.phases[1].rddata[1*databits+j].eq(dq_i_data[1]),
 480                         dfi.phases[1].rddata[2*databits+j].eq(dq_i_data[2]),
 481                         dfi.phases[1].rddata[3*databits+j].eq(dq_i_data[3]),
 482                     ]
 483
 484         # Read Control Path ------------------------------------------------------------------------
 485         # Creates a shift register of read commands coming from the DFI interface. This shift register
 486         # is used to control DQS read (internal read pulse of the DQSBUF) and to indicate to the
 487         # DFI interface that the read data is valid.
 488         #
 489         # The DQS read must be asserted for 2 sys_clk cycles before the read data is coming back from
 490         # the DRAM (see 6.2.4 READ Pulse Positioning Optimization of FPGA-TN-02035-1.2)
 491         #
 492         # The read data valid is asserted for 1 sys_clk cycle when the data is available on the DFI
 493         # interface, the latency is the sum of the ODDRX2DQA, CAS, IDDRX2DQA latencies.
 494         rddata_en = Signal(self.settings.read_latency)
 495         rddata_en_last = Signal.like(rddata_en)
 496         m.d.comb += rddata_en.eq(Cat(dfi.phases[self.settings.rdphase].rddata_en, rddata_en_last))
 497         m.d.sync += rddata_en_last.eq(rddata_en)
 498         m.d.comb += dqs_re.eq(rddata_en[cl_sys_latency + 1] | rddata_en[cl_sys_latency + 2])
 499
 500         rddata_valid = Signal()
 501         m.d.sync += rddata_valid.eq(datavalid_prev & ~datavalid)
 502         for phase in dfi.phases:
 503             m.d.comb += phase.rddata_valid.eq(rddata_valid)
 504
 505         # Write Control Path -----------------------------------------------------------------------
 506         # Creates a shift register of write commands coming from the DFI interface. This shift register
 507         # is used to control DQ/DQS tristates and to select write data of the DRAM burst from the DFI
 508         # interface: The PHY is operating in halfrate mode (so provide 4 datas every sys_clk cycles:
 509         # 2x for DDR, 2x for halfrate) but DDR3 requires a burst of 8 datas (BL8) for best efficiency.
 510         # Writes are then performed in 2 sys_clk cycles and data needs to be selected for each cycle.
 511         # FIXME: understand +2
 512         wrdata_en = Signal(cwl_sys_latency + 4)
 513         wrdata_en_last = Signal.like(wrdata_en)
 514         m.d.comb += wrdata_en.eq(Cat(dfi.phases[self.settings.wrphase].wrdata_en, wrdata_en_last))
 515         m.d.sync += wrdata_en_last.eq(wrdata_en)
 516         m.d.comb += dq_oe.eq(wrdata_en[cwl_sys_latency + 1] | wrdata_en[cwl_sys_latency + 2])
 517         m.d.comb += bl8_chunk.eq(wrdata_en[cwl_sys_latency + 1])
 518         m.d.comb += dqs_oe.eq(dq_oe)
 519
 520         # Write DQS Postamble/Preamble Control Path ------------------------------------------------
 521         # Generates DQS Preamble 1 cycle before the first write and Postamble 1 cycle after the last
 522         # write. During writes, DQS tristate is configured as output for at least 4 sys_clk cycles:
 523         # 1 for Preamble, 2 for the Write and 1 for the Postamble.
 524         m.d.comb += dqs_preamble.eq(wrdata_en[cwl_sys_latency + 0] & ~wrdata_en[cwl_sys_latency + 1])
 525         m.d.comb += dqs_postamble.eq(wrdata_en[cwl_sys_latency + 3] & ~wrdata_en[cwl_sys_latency + 2])
 526
 527         return m