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add 1024M_ddr3_parameters.vh for MT41K64M16
[gram.git] / gram / simulation / dram_model / 1024Mb_ddr3_parameters.vh
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24 * Copyright 2003 Micron Technology, Inc. All rights reserved.
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26 ****************************************************************************************/
27
28 // Timing parameters based on 1Gb_DDR3_SDRAM.cdf - Rev. L 09/12 EN
29
30 // SYMBOL UNITS DESCRIPTION
31 // ------ ----- -----------
32 `ifdef sg093 // sg093 is equivalent to the JEDEC DDR3-2133 (14-14-14) speed bin
33 parameter TCK_MIN = 938; // tCK ps Minimum Clock Cycle Time
34 parameter TJIT_PER = 50; // tJIT(per) ps Period JItter
35 parameter TJIT_CC = 100; // tJIT(cc) ps Cycle to Cycle jitter
36 parameter TERR_2PER = 74; // tERR(2per) ps Accumulated Error (2-cycle)
37 parameter TERR_3PER = 87; // tERR(3per) ps Accumulated Error (3-cycle)
38 parameter TERR_4PER = 97; // tERR(4per) ps Accumulated Error (4-cycle)
39 parameter TERR_5PER = 105; // tERR(5per) ps Accumulated Error (5-cycle)
40 parameter TERR_6PER = 111; // tERR(6per) ps Accumulated Error (6-cycle)
41 parameter TERR_7PER = 116; // tERR(7per) ps Accumulated Error (7-cycle)
42 parameter TERR_8PER = 121; // tERR(8per) ps Accumulated Error (8-cycle)
43 parameter TERR_9PER = 125; // tERR(9per) ps Accumulated Error (9-cycle)
44 parameter TERR_10PER = 128; // tERR(10per)ps Accumulated Error (10-cycle)
45 parameter TERR_11PER = 132; // tERR(11per)ps Accumulated Error (11-cycle)
46 parameter TERR_12PER = 134; // tERR(12per)ps Accumulated Error (12-cycle)
47 parameter TDS = 5; // tDS ps DQ and DM input setup time relative to DQS
48 parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS
49 parameter TDQSQ = 70; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
50 parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
51 parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time)
52 parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time)
53 parameter TDQSCK = 180; // tDQSCK ps DQS output access time from CK/CK#
54 parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width
55 parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width
56 parameter TDIPW = 280; // tDIPW ps DQ and DM input Pulse Width
57 parameter TIPW = 470; // tIPW ps Control and Address input Pulse Width
58 parameter TIS = 35; // tIS ps Input Setup Time
59 parameter TIH = 75; // tIH ps Input Hold Time
60 parameter TRAS_MIN = 33000; // tRAS ps Minimum Active to Precharge command time
61 parameter TRC = 46130; // tRC ps Active to Active/Auto Refresh command time
62 parameter TRCD = 13090; // tRCD ps Active to Read/Write command time
63 parameter TRP = 13090; // tRP ps Precharge command period
64 parameter TXP = 6000; // tXP ps Exit power down to a valid command
65 parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width
66 parameter TAON = 180; // tAON ps RTT turn-on from ODTLon reference
67 parameter TWLS = 122; // tWLS ps Setup time for tDQS flop
68 parameter TWLH = 122; // tWLH ps Hold time of tDQS flop
69 parameter TWLO = 7500; // tWLO ps Write levelization output delay
70 parameter TAA_MIN = 13090; // TAA ps Internal READ command to first data
71 parameter CL_TIME = 13090; // CL ps Minimum CAS Latency
72 `elsif sg107 // sg107 is equivalent to the JEDEC DDR3-1866 (13-13-13) speed bin
73 parameter TCK_MIN = 1071; // tCK ps Minimum Clock Cycle Time
74 parameter TJIT_PER = 60; // tJIT(per) ps Period JItter
75 parameter TJIT_CC = 120; // tJIT(cc) ps Cycle to Cycle jitter
76 parameter TERR_2PER = 88; // tERR(2per) ps Accumulated Error (2-cycle)
77 parameter TERR_3PER = 105; // tERR(3per) ps Accumulated Error (3-cycle)
78 parameter TERR_4PER = 117; // tERR(4per) ps Accumulated Error (4-cycle)
79 parameter TERR_5PER = 126; // tERR(5per) ps Accumulated Error (5-cycle)
80 parameter TERR_6PER = 133; // tERR(6per) ps Accumulated Error (6-cycle)
81 parameter TERR_7PER = 139; // tERR(7per) ps Accumulated Error (7-cycle)
82 parameter TERR_8PER = 145; // tERR(8per) ps Accumulated Error (8-cycle)
83 parameter TERR_9PER = 150; // tERR(9per) ps Accumulated Error (9-cycle)
84 parameter TERR_10PER = 154; // tERR(10per)ps Accumulated Error (10-cycle)
85 parameter TERR_11PER = 158; // tERR(11per)ps Accumulated Error (11-cycle)
86 parameter TERR_12PER = 161; // tERR(12per)ps Accumulated Error (12-cycle)
87 parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS
88 parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS
89 parameter TDQSQ = 80; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
90 parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
91 parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time)
92 parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time)
93 parameter TDQSCK = 200; // tDQSCK ps DQS output access time from CK/CK#
94 parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width
95 parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width
96 parameter TDIPW = 320; // tDIPW ps DQ and DM input Pulse Width
97 parameter TIPW = 535; // tIPW ps Control and Address input Pulse Width
98 parameter TIS = 50; // tIS ps Input Setup Time
99 parameter TIH = 100; // tIH ps Input Hold Time
100 parameter TRAS_MIN = 34000; // tRAS ps Minimum Active to Precharge command time
101 parameter TRC = 48910; // tRC ps Active to Active/Auto Refresh command time
102 parameter TRCD = 13910; // tRCD ps Active to Read/Write command time
103 parameter TRP = 13910; // tRP ps Precharge command period
104 parameter TXP = 6000; // tXP ps Exit power down to a valid command
105 parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width
106 parameter TAON = 200; // tAON ps RTT turn-on from ODTLon reference
107 parameter TWLS = 140; // tWLS ps Setup time for tDQS flop
108 parameter TWLH = 140; // tWLH ps Hold time of tDQS flop
109 parameter TWLO = 7500; // tWLO ps Write levelization output delay
110 parameter TAA_MIN = 13910; // TAA ps Internal READ command to first data
111 parameter CL_TIME = 13910; // CL ps Minimum CAS Latency
112 `elsif sg125 // sg125 is equivalent to the JEDEC DDR3-1600 (11-11-11) speed bin
113 parameter TCK_MIN = 1250; // tCK ps Minimum Clock Cycle Time
114 parameter TJIT_PER = 70; // tJIT(per) ps Period JItter
115 parameter TJIT_CC = 140; // tJIT(cc) ps Cycle to Cycle jitter
116 parameter TERR_2PER = 103; // tERR(2per) ps Accumulated Error (2-cycle)
117 parameter TERR_3PER = 122; // tERR(3per) ps Accumulated Error (3-cycle)
118 parameter TERR_4PER = 136; // tERR(4per) ps Accumulated Error (4-cycle)
119 parameter TERR_5PER = 147; // tERR(5per) ps Accumulated Error (5-cycle)
120 parameter TERR_6PER = 155; // tERR(6per) ps Accumulated Error (6-cycle)
121 parameter TERR_7PER = 163; // tERR(7per) ps Accumulated Error (7-cycle)
122 parameter TERR_8PER = 169; // tERR(8per) ps Accumulated Error (8-cycle)
123 parameter TERR_9PER = 175; // tERR(9per) ps Accumulated Error (9-cycle)
124 parameter TERR_10PER = 180; // tERR(10per)ps Accumulated Error (10-cycle)
125 parameter TERR_11PER = 184; // tERR(11per)ps Accumulated Error (11-cycle)
126 parameter TERR_12PER = 188; // tERR(12per)ps Accumulated Error (12-cycle)
127 parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS
128 parameter TDH = 45; // tDH ps DQ and DM input hold time relative to DQS
129 parameter TDQSQ = 100; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
130 parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
131 parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time)
132 parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time)
133 parameter TDQSCK = 225; // tDQSCK ps DQS output access time from CK/CK#
134 parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width
135 parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width
136 parameter TDIPW = 360; // tDIPW ps DQ and DM input Pulse Width
137 parameter TIPW = 560; // tIPW ps Control and Address input Pulse Width
138 parameter TIS = 170; // tIS ps Input Setup Time
139 parameter TIH = 120; // tIH ps Input Hold Time
140 parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time
141 parameter TRC = 48750; // tRC ps Active to Active/Auto Refresh command time
142 parameter TRCD = 13750; // tRCD ps Active to Read/Write command time
143 parameter TRP = 13750; // tRP ps Precharge command period
144 parameter TXP = 6000; // tXP ps Exit power down to a valid command
145 parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width
146 parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference
147 parameter TWLS = 165; // tWLS ps Setup time for tDQS flop
148 parameter TWLH = 165; // tWLH ps Hold time of tDQS flop
149 parameter TWLO = 7500; // tWLO ps Write levelization output delay
150 parameter TAA_MIN = 13750; // TAA ps Internal READ command to first data
151 parameter CL_TIME = 13750; // CL ps Minimum CAS Latency
152 `elsif sg15E // sg15E is equivalent to the JEDEC DDR3-1333H (9-9-9) speed bin
153 parameter TCK_MIN = 1500; // tCK ps Minimum Clock Cycle Time
154 parameter TJIT_PER = 80; // tJIT(per) ps Period JItter
155 parameter TJIT_CC = 160; // tJIT(cc) ps Cycle to Cycle jitter
156 parameter TERR_2PER = 118; // tERR(2per) ps Accumulated Error (2-cycle)
157 parameter TERR_3PER = 140; // tERR(3per) ps Accumulated Error (3-cycle)
158 parameter TERR_4PER = 155; // tERR(4per) ps Accumulated Error (4-cycle)
159 parameter TERR_5PER = 168; // tERR(5per) ps Accumulated Error (5-cycle)
160 parameter TERR_6PER = 177; // tERR(6per) ps Accumulated Error (6-cycle)
161 parameter TERR_7PER = 186; // tERR(7per) ps Accumulated Error (7-cycle)
162 parameter TERR_8PER = 193; // tERR(8per) ps Accumulated Error (8-cycle)
163 parameter TERR_9PER = 200; // tERR(9per) ps Accumulated Error (9-cycle)
164 parameter TERR_10PER = 205; // tERR(10per)ps Accumulated Error (10-cycle)
165 parameter TERR_11PER = 210; // tERR(11per)ps Accumulated Error (11-cycle)
166 parameter TERR_12PER = 215; // tERR(12per)ps Accumulated Error (12-cycle)
167 parameter TDS = 30; // tDS ps DQ and DM input setup time relative to DQS
168 parameter TDH = 65; // tDH ps DQ and DM input hold time relative to DQS
169 parameter TDQSQ = 125; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
170 parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
171 parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time)
172 parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time)
173 parameter TDQSCK = 255; // tDQSCK ps DQS output access time from CK/CK#
174 parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width
175 parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width
176 parameter TDIPW = 400; // tDIPW ps DQ and DM input Pulse Width
177 parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width
178 parameter TIS = 190; // tIS ps Input Setup Time
179 parameter TIH = 140; // tIH ps Input Hold Time
180 parameter TRAS_MIN = 36000; // tRAS ps Minimum Active to Precharge command time
181 parameter TRC = 49500; // tRC ps Active to Active/Auto Refresh command time
182 parameter TRCD = 13500; // tRCD ps Active to Read/Write command time
183 parameter TRP = 13500; // tRP ps Precharge command period
184 parameter TXP = 6000; // tXP ps Exit power down to a valid command
185 parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width
186 parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference
187 parameter TWLS = 195; // tWLS ps Setup time for tDQS flop
188 parameter TWLH = 195; // tWLH ps Hold time of tDQS flop
189 parameter TWLO = 9000; // tWLO ps Write levelization output delay
190 parameter TAA_MIN = 13500; // TAA ps Internal READ command to first data
191 parameter CL_TIME = 13500; // CL ps Minimum CAS Latency
192 `elsif sg15 // sg15 is equivalent to the JEDEC DDR3-1333J (10-10-10) speed bin
193 parameter TCK_MIN = 1500; // tCK ps Minimum Clock Cycle Time
194 parameter TJIT_PER = 80; // tJIT(per) ps Period JItter
195 parameter TJIT_CC = 160; // tJIT(cc) ps Cycle to Cycle jitter
196 parameter TERR_2PER = 118; // tERR(2per) ps Accumulated Error (2-cycle)
197 parameter TERR_3PER = 140; // tERR(3per) ps Accumulated Error (3-cycle)
198 parameter TERR_4PER = 155; // tERR(4per) ps Accumulated Error (4-cycle)
199 parameter TERR_5PER = 168; // tERR(5per) ps Accumulated Error (5-cycle)
200 parameter TERR_6PER = 177; // tERR(6per) ps Accumulated Error (6-cycle)
201 parameter TERR_7PER = 186; // tERR(7per) ps Accumulated Error (7-cycle)
202 parameter TERR_8PER = 193; // tERR(8per) ps Accumulated Error (8-cycle)
203 parameter TERR_9PER = 200; // tERR(9per) ps Accumulated Error (9-cycle)
204 parameter TERR_10PER = 205; // tERR(10per)ps Accumulated Error (10-cycle)
205 parameter TERR_11PER = 210; // tERR(11per)ps Accumulated Error (11-cycle)
206 parameter TERR_12PER = 215; // tERR(12per)ps Accumulated Error (12-cycle)
207 parameter TDS = 30; // tDS ps DQ and DM input setup time relative to DQS
208 parameter TDH = 65; // tDH ps DQ and DM input hold time relative to DQS
209 parameter TDQSQ = 125; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
210 parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
211 parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time)
212 parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time)
213 parameter TDQSCK = 255; // tDQSCK ps DQS output access time from CK/CK#
214 parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width
215 parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width
216 parameter TDIPW = 400; // tDIPW ps DQ and DM input Pulse Width
217 parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width
218 parameter TIS = 190; // tIS ps Input Setup Time
219 parameter TIH = 140; // tIH ps Input Hold Time
220 parameter TRAS_MIN = 36000; // tRAS ps Minimum Active to Precharge command time
221 parameter TRC = 51000; // tRC ps Active to Active/Auto Refresh command time
222 parameter TRCD = 15000; // tRCD ps Active to Read/Write command time
223 parameter TRP = 15000; // tRP ps Precharge command period
224 parameter TXP = 6000; // tXP ps Exit power down to a valid command
225 parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width
226 parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference
227 parameter TWLS = 195; // tWLS ps Setup time for tDQS flop
228 parameter TWLH = 195; // tWLH ps Hold time of tDQS flop
229 parameter TWLO = 9000; // tWLO ps Write levelization output delay
230 parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data
231 parameter CL_TIME = 15000; // CL ps Minimum CAS Latency
232 `elsif sg187E // sg187E is equivalent to the JEDEC DDR3-1066F (7-7-7) speed bin
233 parameter TCK_MIN = 1875; // tCK ps Minimum Clock Cycle Time
234 parameter TJIT_PER = 90; // tJIT(per) ps Period JItter
235 parameter TJIT_CC = 180; // tJIT(cc) ps Cycle to Cycle jitter
236 parameter TERR_2PER = 132; // tERR(2per) ps Accumulated Error (2-cycle)
237 parameter TERR_3PER = 157; // tERR(3per) ps Accumulated Error (3-cycle)
238 parameter TERR_4PER = 175; // tERR(4per) ps Accumulated Error (4-cycle)
239 parameter TERR_5PER = 188; // tERR(5per) ps Accumulated Error (5-cycle)
240 parameter TERR_6PER = 200; // tERR(6per) ps Accumulated Error (6-cycle)
241 parameter TERR_7PER = 209; // tERR(7per) ps Accumulated Error (7-cycle)
242 parameter TERR_8PER = 217; // tERR(8per) ps Accumulated Error (8-cycle)
243 parameter TERR_9PER = 224; // tERR(9per) ps Accumulated Error (9-cycle)
244 parameter TERR_10PER = 231; // tERR(10per)ps Accumulated Error (10-cycle)
245 parameter TERR_11PER = 237; // tERR(11per)ps Accumulated Error (11-cycle)
246 parameter TERR_12PER = 242; // tERR(12per)ps Accumulated Error (12-cycle)
247 parameter TDS = 75; // tDS ps DQ and DM input setup time relative to DQS
248 parameter TDH = 100; // tDH ps DQ and DM input hold time relative to DQS
249 parameter TDQSQ = 150; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
250 parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
251 parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time)
252 parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time)
253 parameter TDQSCK = 300; // tDQSCK ps DQS output access time from CK/CK#
254 parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width
255 parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width
256 parameter TDIPW = 490; // tDIPW ps DQ and DM input Pulse Width
257 parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width
258 parameter TIS = 275; // tIS ps Input Setup Time
259 parameter TIH = 200; // tIH ps Input Hold Time
260 parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time
261 parameter TRC = 50625; // tRC ps Active to Active/Auto Refresh command time
262 parameter TRCD = 13125; // tRCD ps Active to Read/Write command time
263 parameter TRP = 13125; // tRP ps Precharge command period
264 parameter TXP = 7500; // tXP ps Exit power down to a valid command
265 parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width
266 parameter TAON = 300; // tAON ps RTT turn-on from ODTLon reference
267 parameter TWLS = 245; // tWLS ps Setup time for tDQS flop
268 parameter TWLH = 245; // tWLH ps Hold time of tDQS flop
269 parameter TWLO = 9000; // tWLO ps Write levelization output delay
270 parameter TAA_MIN = 13125; // TAA ps Internal READ command to first data
271 parameter CL_TIME = 13125; // CL ps Minimum CAS Latency
272 `elsif sg187 // sg187 is equivalent to the JEDEC DDR3-1066G (8-8-8) speed bin
273 parameter TCK_MIN = 1875; // tCK ps Minimum Clock Cycle Time
274 parameter TJIT_PER = 90; // tJIT(per) ps Period JItter
275 parameter TJIT_CC = 180; // tJIT(cc) ps Cycle to Cycle jitter
276 parameter TERR_2PER = 132; // tERR(2per) ps Accumulated Error (2-cycle)
277 parameter TERR_3PER = 157; // tERR(3per) ps Accumulated Error (3-cycle)
278 parameter TERR_4PER = 175; // tERR(4per) ps Accumulated Error (4-cycle)
279 parameter TERR_5PER = 188; // tERR(5per) ps Accumulated Error (5-cycle)
280 parameter TERR_6PER = 200; // tERR(6per) ps Accumulated Error (6-cycle)
281 parameter TERR_7PER = 209; // tERR(7per) ps Accumulated Error (7-cycle)
282 parameter TERR_8PER = 217; // tERR(8per) ps Accumulated Error (8-cycle)
283 parameter TERR_9PER = 224; // tERR(9per) ps Accumulated Error (9-cycle)
284 parameter TERR_10PER = 231; // tERR(10per)ps Accumulated Error (10-cycle)
285 parameter TERR_11PER = 237; // tERR(11per)ps Accumulated Error (11-cycle)
286 parameter TERR_12PER = 242; // tERR(12per)ps Accumulated Error (12-cycle)
287 parameter TDS = 75; // tDS ps DQ and DM input setup time relative to DQS
288 parameter TDH = 100; // tDH ps DQ and DM input hold time relative to DQS
289 parameter TDQSQ = 150; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
290 parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
291 parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time)
292 parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time)
293 parameter TDQSCK = 300; // tDQSCK ps DQS output access time from CK/CK#
294 parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width
295 parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width
296 parameter TDIPW = 490; // tDIPW ps DQ and DM input Pulse Width
297 parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width
298 parameter TIS = 275; // tIS ps Input Setup Time
299 parameter TIH = 200; // tIH ps Input Hold Time
300 parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time
301 parameter TRC = 52500; // tRC ps Active to Active/Auto Refresh command time
302 parameter TRCD = 15000; // tRCD ps Active to Read/Write command time
303 parameter TRP = 15000; // tRP ps Precharge command period
304 parameter TXP = 7500; // tXP ps Exit power down to a valid command
305 parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width
306 parameter TAON = 300; // tAON ps RTT turn-on from ODTLon reference
307 parameter TWLS = 245; // tWLS ps Setup time for tDQS flop
308 parameter TWLH = 245; // tWLH ps Hold time of tDQS flop
309 parameter TWLO = 9000; // tWLO ps Write levelization output delay
310 parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data
311 parameter CL_TIME = 15000; // CL ps Minimum CAS Latency
312 `elsif sg25E // sg25E is equivalent to the JEDEC DDR3-800E (5-5-5) speed bin
313 parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time
314 parameter TJIT_PER = 100; // tJIT(per) ps Period JItter
315 parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter
316 parameter TERR_2PER = 147; // tERR(2per) ps Accumulated Error (2-cycle)
317 parameter TERR_3PER = 175; // tERR(3per) ps Accumulated Error (3-cycle)
318 parameter TERR_4PER = 194; // tERR(4per) ps Accumulated Error (4-cycle)
319 parameter TERR_5PER = 209; // tERR(5per) ps Accumulated Error (5-cycle)
320 parameter TERR_6PER = 222; // tERR(6per) ps Accumulated Error (6-cycle)
321 parameter TERR_7PER = 232; // tERR(7per) ps Accumulated Error (7-cycle)
322 parameter TERR_8PER = 241; // tERR(8per) ps Accumulated Error (8-cycle)
323 parameter TERR_9PER = 249; // tERR(9per) ps Accumulated Error (9-cycle)
324 parameter TERR_10PER = 257; // tERR(10per)ps Accumulated Error (10-cycle)
325 parameter TERR_11PER = 263; // tERR(11per)ps Accumulated Error (11-cycle)
326 parameter TERR_12PER = 269; // tERR(12per)ps Accumulated Error (12-cycle)
327 parameter TDS = 125; // tDS ps DQ and DM input setup time relative to DQS
328 parameter TDH = 150; // tDH ps DQ and DM input hold time relative to DQS
329 parameter TDQSQ = 200; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
330 parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
331 parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time)
332 parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time)
333 parameter TDQSCK = 400; // tDQSCK ps DQS output access time from CK/CK#
334 parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width
335 parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width
336 parameter TDIPW = 600; // tDIPW ps DQ and DM input Pulse Width
337 parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width
338 parameter TIS = 350; // tIS ps Input Setup Time
339 parameter TIH = 275; // tIH ps Input Hold Time
340 parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time
341 parameter TRC = 50000; // tRC ps Active to Active/Auto Refresh command time
342 parameter TRCD = 12500; // tRCD ps Active to Read/Write command time
343 parameter TRP = 12500; // tRP ps Precharge command period
344 parameter TXP = 7500; // tXP ps Exit power down to a valid command
345 parameter TCKE = 7500; // tCKE ps CKE minimum high or low pulse width
346 parameter TAON = 400; // tAON ps RTT turn-on from ODTLon reference
347 parameter TWLS = 325; // tWLS ps Setup time for tDQS flop
348 parameter TWLH = 325; // tWLH ps Hold time of tDQS flop
349 parameter TWLO = 9000; // tWLO ps Write levelization output delay
350 parameter TAA_MIN = 12500; // TAA ps Internal READ command to first data
351 parameter CL_TIME = 12500; // CL ps Minimum CAS Latency
352 `else
353 `define sg25 // sg25 is equivalent to the JEDEC DDR3-800 (6-6-6) speed bin
354 parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time
355 parameter TJIT_PER = 100; // tJIT(per) ps Period JItter
356 parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter
357 parameter TERR_2PER = 147; // tERR(2per) ps Accumulated Error (2-cycle)
358 parameter TERR_3PER = 175; // tERR(3per) ps Accumulated Error (3-cycle)
359 parameter TERR_4PER = 194; // tERR(4per) ps Accumulated Error (4-cycle)
360 parameter TERR_5PER = 209; // tERR(5per) ps Accumulated Error (5-cycle)
361 parameter TERR_6PER = 222; // tERR(6per) ps Accumulated Error (6-cycle)
362 parameter TERR_7PER = 232; // tERR(7per) ps Accumulated Error (7-cycle)
363 parameter TERR_8PER = 241; // tERR(8per) ps Accumulated Error (8-cycle)
364 parameter TERR_9PER = 249; // tERR(9per) ps Accumulated Error (9-cycle)
365 parameter TERR_10PER = 257; // tERR(10per)ps Accumulated Error (10-cycle)
366 parameter TERR_11PER = 263; // tERR(11per)ps Accumulated Error (11-cycle)
367 parameter TERR_12PER = 269; // tERR(12per)ps Accumulated Error (12-cycle)
368 parameter TDS = 125; // tDS ps DQ and DM input setup time relative to DQS
369 parameter TDH = 150; // tDH ps DQ and DM input hold time relative to DQS
370 parameter TDQSQ = 200; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
371 parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
372 parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time)
373 parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time)
374 parameter TDQSCK = 400; // tDQSCK ps DQS output access time from CK/CK#
375 parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width
376 parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width
377 parameter TDIPW = 600; // tDIPW ps DQ and DM input Pulse Width
378 parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width
379 parameter TIS = 350; // tIS ps Input Setup Time
380 parameter TIH = 275; // tIH ps Input Hold Time
381 parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time
382 parameter TRC = 52500; // tRC ps Active to Active/Auto Refresh command time
383 parameter TRCD = 15000; // tRCD ps Active to Read/Write command time
384 parameter TRP = 15000; // tRP ps Precharge command period
385 parameter TXP = 7500; // tXP ps Exit power down to a valid command
386 parameter TCKE = 7500; // tCKE ps CKE minimum high or low pulse width
387 parameter TAON = 400; // tAON ps RTT turn-on from ODTLon reference
388 parameter TWLS = 325; // tWLS ps Setup time for tDQS flop
389 parameter TWLH = 325; // tWLH ps Hold time of tDQS flop
390 parameter TWLO = 9000; // tWLO ps Write levelization output delay
391 parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data
392 parameter CL_TIME = 15000; // CL ps Minimum CAS Latency
393 `endif
394
395 parameter TDQSCK_DLLDIS = TDQSCK; // tDQSCK ps for DLLDIS mode, timing not guaranteed
396
397 `ifdef x16
398 `ifdef sg093
399 parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time
400 parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window
401 `elsif sg107
402 parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time
403 parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window
404 `elsif sg125
405 parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time
406 parameter TFAW = 40000; // tFAW ps (2KB page size) Four Bank Activate window
407 `elsif sg15E
408 parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time
409 parameter TFAW = 45000; // tFAW ps (2KB page size) Four Bank Activate window
410 `elsif sg15
411 parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time
412 parameter TFAW = 45000; // tFAW ps (2KB page size) Four Bank Activate window
413 `elsif sg187E
414 parameter TRRD = 10000; // tRRD ps (2KB page size) Active bank a to Active bank b command time
415 parameter TFAW = 50000; // tFAW ps (2KB page size) Four Bank Activate window
416 `elsif sg187
417 parameter TRRD = 10000; // tRRD ps (2KB page size) Active bank a to Active bank b command time
418 parameter TFAW = 50000; // tFAW ps (2KB page size) Four Bank Activate window
419 `elsif sg25E
420 parameter TRRD = 10000; // tRRD ps (2KB page size) Active bank a to Active bank b command time
421 parameter TFAW = 50000; // tFAW ps (2KB page size) Four Bank Activate window
422 `else // sg25
423 parameter TRRD = 10000; // tRRD ps (2KB page size) Active bank a to Active bank b command time
424 parameter TFAW = 50000; // tFAW ps (2KB page size) Four Bank Activate window
425 `endif
426 `else // x4, x8
427 `ifdef sg093
428 parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time
429 parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window
430 `elsif sg107
431 parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time
432 parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window
433 `elsif sg125
434 parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time
435 parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window
436 `elsif sg15E
437 parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time
438 parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window
439 `elsif sg15
440 parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time
441 parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window
442 `elsif sg187E
443 parameter TRRD = 7500; // tRRD ps (1KB page size) Active bank a to Active bank b command time
444 parameter TFAW = 37500; // tFAW ps (1KB page size) Four Bank Activate window
445 `elsif sg187
446 parameter TRRD = 7500; // tRRD ps (1KB page size) Active bank a to Active bank b command time
447 parameter TFAW = 37500; // tFAW ps (1KB page size) Four Bank Activate window
448 `elsif sg25E
449 parameter TRRD = 10000; // tRRD ps (1KB page size) Active bank a to Active bank b command time
450 parameter TFAW = 40000; // tFAW ps (1KB page size) Four Bank Activate window
451 `else // sg25
452 parameter TRRD = 10000; // tRRD ps (1KB page size) Active bank a to Active bank b command time
453 parameter TFAW = 40000; // tFAW ps (1KB page size) Four Bank Activate window
454 `endif
455 `endif
456
457 // Timing Parameters
458
459 // Mode Register
460 parameter CL_MIN = 5; // CL tCK Minimum CAS Latency
461 parameter CL_MAX = 14; // CL tCK Maximum CAS Latency
462 parameter AL_MIN = 0; // AL tCK Minimum Additive Latency
463 parameter AL_MAX = 2; // AL tCK Maximum Additive Latency
464 parameter WR_MIN = 5; // WR tCK Minimum Write Recovery
465 parameter WR_MAX = 16; // WR tCK Maximum Write Recovery
466 parameter BL_MIN = 4; // BL tCK Minimum Burst Length
467 parameter BL_MAX = 8; // BL tCK Minimum Burst Length
468 parameter CWL_MIN = 5; // CWL tCK Minimum CAS Write Latency
469 parameter CWL_MAX = 10; // CWL tCK Maximum CAS Write Latency
470
471 // Clock
472 parameter TCK_MAX = 3300; // tCK ps Maximum Clock Cycle Time
473 parameter TCH_AVG_MIN = 0.47; // tCH tCK Minimum Clock High-Level Pulse Width
474 parameter TCL_AVG_MIN = 0.47; // tCL tCK Minimum Clock Low-Level Pulse Width
475 parameter TCH_AVG_MAX = 0.53; // tCH tCK Maximum Clock High-Level Pulse Width
476 parameter TCL_AVG_MAX = 0.53; // tCL tCK Maximum Clock Low-Level Pulse Width
477 parameter TCH_ABS_MIN = 0.43; // tCH tCK Minimum Clock High-Level Pulse Width
478 parameter TCL_ABS_MIN = 0.43; // tCL tCK Maximum Clock Low-Level Pulse Width
479 parameter TCKE_TCK = 3; // tCKE tCK CKE minimum high or low pulse width
480 parameter TAA_MAX = 20000; // TAA ps Internal READ command to first data
481
482 // Data OUT
483 parameter TQH = 0.38; // tQH ps DQ output hold time from DQS, DQS#
484 // Data Strobe OUT
485 parameter TRPRE = 0.90; // tRPRE tCK DQS Read Preamble
486 parameter TRPST = 0.30; // tRPST tCK DQS Read Postamble
487 // Data Strobe IN
488 parameter TDQSH = 0.45; // tDQSH tCK DQS input High Pulse Width
489 parameter TDQSL = 0.45; // tDQSL tCK DQS input Low Pulse Width
490 parameter TWPRE = 0.90; // tWPRE tCK DQS Write Preamble
491 parameter TWPST = 0.30; // tWPST tCK DQS Write Postamble
492 // Command and Address
493 integer TZQCS; // tZQCS tCK ZQ Cal (Short) time
494 integer TZQINIT; // tZQinit tCK ZQ Cal (Long) time
495 integer TZQOPER; // tZQoper tCK ZQ Cal (Long) time
496 parameter TCCD = 4; // tCCD tCK Cas to Cas command delay
497 parameter TCCD_DG = 2; // tCCD_DG tCK Cas to Cas command delay to different group
498 parameter TRAS_MAX = 60e9; // tRAS ps Maximum Active to Precharge command time
499 parameter TWR = 15000; // tWR ps Write recovery time
500 parameter TMRD = 4; // tMRD tCK Load Mode Register command cycle time
501 parameter TMOD = 15000; // tMOD ps LOAD MODE to non-LOAD MODE command cycle time
502 parameter TMOD_TCK = 12; // tMOD tCK LOAD MODE to non-LOAD MODE command cycle time
503 parameter TRRD_TCK = 4; // tRRD tCK Active bank a to Active bank b command time
504 parameter TRRD_DG = 3000; // tRRD_DG ps Active bank a to Active bank b command time to different group
505 parameter TRRD_DG_TCK = 2; // tRRD_DG tCK Active bank a to Active bank b command time to different group
506 parameter TRTP = 7500; // tRTP ps Read to Precharge command delay
507 parameter TRTP_TCK = 4; // tRTP tCK Read to Precharge command delay
508 parameter TWTR = 7500; // tWTR ps Write to Read command delay
509 parameter TWTR_DG = 3750; // tWTR_DG ps Write to Read command delay to different group
510 parameter TWTR_TCK = 4; // tWTR tCK Write to Read command delay
511 parameter TWTR_DG_TCK = 2; // tWTR_DG tCK Write to Read command delay to different group
512 parameter TDLLK = 512; // tDLLK tCK DLL locking time
513 // Refresh - 1Gb
514 parameter TRFC_MIN = 110000; // tRFC ps Refresh to Refresh Command interval minimum value
515 parameter TRFC_MAX =70200000; // tRFC ps Refresh to Refresh Command Interval maximum value
516 // Power Down
517 parameter TXP_TCK = 3; // tXP tCK Exit power down to a valid command
518 parameter TXPDLL = 24000; // tXPDLL ps Exit precharge power down to READ or WRITE command (DLL-off mode)
519 parameter TXPDLL_TCK = 10; // tXPDLL tCK Exit precharge power down to READ or WRITE command (DLL-off mode)
520 parameter TACTPDEN = 1; // tACTPDEN tCK Timing of last ACT command to power down entry
521 parameter TPRPDEN = 1; // tPREPDEN tCK Timing of last PRE command to power down entry
522 parameter TREFPDEN = 1; // tARPDEN tCK Timing of last REFRESH command to power down entry
523 parameter TCPDED = 1; // tCPDED tCK Command pass disable/enable delay
524 parameter TPD_MAX =TRFC_MAX; // tPD ps Power-down entry-to-exit timing
525 parameter TXPR = 120000; // tXPR ps Exit Reset from CKE assertion to a valid command
526 parameter TXPR_TCK = 5; // tXPR tCK Exit Reset from CKE assertion to a valid command
527 // Self Refresh
528 parameter TXS = 120000; // tXS ps Exit self refesh to a non-read or write command
529 parameter TXS_TCK = 5; // tXS tCK Exit self refesh to a non-read or write command
530 parameter TXSDLL = TDLLK; // tXSRD tCK Exit self refresh to a read or write command
531 parameter TISXR = TIS; // tISXR ps CKE setup time during self refresh exit.
532 parameter TCKSRE = 10000; // tCKSRE ps Valid Clock requirement after self refresh entry (SRE)
533 parameter TCKSRE_TCK = 5; // tCKSRE tCK Valid Clock requirement after self refresh entry (SRE)
534 parameter TCKSRX = 10000; // tCKSRX ps Valid Clock requirement prior to self refresh exit (SRX)
535 parameter TCKSRX_TCK = 5; // tCKSRX tCK Valid Clock requirement prior to self refresh exit (SRX)
536 parameter TCKESR_TCK = 4; // tCKESR tCK Minimum CKE low width for Self Refresh entry to exit timing
537 // ODT
538 parameter TAOF = 0.7; // tAOF tCK RTT turn-off from ODTLoff reference
539 parameter TAONPD = 8500; // tAONPD ps Asynchronous RTT turn-on delay (Power-Down with DLL frozen)
540 parameter TAOFPD = 8500; // tAONPD ps Asynchronous RTT turn-off delay (Power-Down with DLL frozen)
541 parameter ODTH4 = 4; // ODTH4 tCK ODT minimum HIGH time after ODT assertion or write (BL4)
542 parameter ODTH8 = 6; // ODTH8 tCK ODT minimum HIGH time after write (BL8)
543 parameter TADC = 0.7; // tADC tCK RTT dynamic change skew
544 // Write Levelization
545 parameter TWLMRD = 40; // tWLMRD tCK First DQS pulse rising edge after tDQSS margining mode is programmed
546 parameter TWLDQSEN = 25; // tWLDQSEN tCK DQS/DQS delay after tDQSS margining mode is programmed
547 parameter TWLOE = 2000; // tWLOE ps Write levelization output error
548
549 // Size Parameters based on Part Width
550
551 `ifdef x4
552 parameter DM_BITS = 1; // Set this parameter to control how many Data Mask bits are used
553 parameter ADDR_BITS = 14; // MAX Address Bits
554 parameter ROW_BITS = 14; // Set this parameter to control how many Address bits are used
555 parameter COL_BITS = 11; // Set this parameter to control how many Column bits are used
556 parameter DQ_BITS = 4; // Set this parameter to control how many Data bits are used **Same as part bit width**
557 parameter DQS_BITS = 1; // Set this parameter to control how many Dqs bits are used
558 `elsif x8
559 parameter DM_BITS = 1; // Set this parameter to control how many Data Mask bits are used
560 parameter ADDR_BITS = 14; // MAX Address Bits
561 parameter ROW_BITS = 14; // Set this parameter to control how many Address bits are used
562 parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used
563 parameter DQ_BITS = 8; // Set this parameter to control how many Data bits are used **Same as part bit width**
564 parameter DQS_BITS = 1; // Set this parameter to control how many Dqs bits are used
565 `else
566 `define x16
567 parameter DM_BITS = 2; // Set this parameter to control how many Data Mask bits are used
568 parameter ADDR_BITS = 13; // MAX Address Bits
569 parameter ROW_BITS = 13; // Set this parameter to control how many Address bits are used
570 parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used
571 parameter DQ_BITS = 16; // Set this parameter to control how many Data bits are used **Same as part bit width**
572 parameter DQS_BITS = 2; // Set this parameter to control how many Dqs bits are used
573 `endif
574
575 // Size Parameters
576 parameter BA_BITS = 3; // Set this parmaeter to control how many Bank Address bits are used
577 parameter MEM_BITS = 10; // Set this parameter to control how many write data bursts can be stored in memory. The default is 2^10=1024.
578 parameter AP = 10; // the address bit that controls auto-precharge and precharge-all
579 parameter BC = 12; // the address bit that controls burst chop
580 parameter BL_BITS = 3; // the number of bits required to count to BL_MAX
581 parameter BO_BITS = 2; // the number of Burst Order Bits
582
583 `ifdef QUAD_RANK
584 parameter CS_BITS = 4; // Number of Chip Select Bits
585 parameter RANKS = 4; // Number of Chip Selects
586 `elsif DUAL_RANK
587 parameter CS_BITS = 2; // Number of Chip Select Bits
588 parameter RANKS = 2; // Number of Chip Selects
589 `else
590 parameter CS_BITS = 1; // Number of Chip Select Bits
591 parameter RANKS = 1; // Number of Chip Selects
592 `endif
593
594 // Simulation parameters
595 parameter RZQ = 240; // termination resistance
596 parameter PRE_DEF_PAT = 8'hAA; // value returned during mpr pre-defined pattern readout
597 parameter STOP_ON_ERROR = 1; // If set to 1, the model will halt on command sequence/major errors
598 parameter DEBUG = 1; // Turn on Debug messages
599 parameter BUS_DELAY = 0; // delay in nanoseconds
600 parameter RANDOM_OUT_DELAY = 0; // If set to 1, the model will put a random amount of delay on DQ/DQS during reads
601 parameter RANDOM_SEED = 31913; //seed value for random generator.
602
603 parameter RDQSEN_PRE = 2; // DQS driving time prior to first read strobe
604 parameter RDQSEN_PST = 1; // DQS driving time after last read strobe
605 parameter RDQS_PRE = 2; // DQS low time prior to first read strobe
606 parameter RDQS_PST = 1; // DQS low time after last read strobe
607 parameter RDQEN_PRE = 0; // DQ/DM driving time prior to first read data
608 parameter RDQEN_PST = 0; // DQ/DM driving time after last read data
609 parameter WDQS_PRE = 2; // DQS half clock periods prior to first write strobe
610 parameter WDQS_PST = 1; // DQS half clock periods after last write strobe
611
612 // check for legal cas latency based on the cas write latency
613 function valid_cl;
614 input [3:0] cl;
615 input [3:0] cwl;
616
617 case ({cwl, cl})
618 `ifdef sg093
619 {4'd5 , 4'd5 },
620 {4'd5 , 4'd6 },
621 {4'd6 , 4'd7 },
622 {4'd6 , 4'd8 },
623 {4'd7 , 4'd9 },
624 {4'd7 , 4'd10},
625 {4'd8 , 4'd11},
626 {4'd9 , 4'd13},
627 {4'd10, 4'd14}: valid_cl = 1;
628 `elsif sg107
629 {4'd5, 4'd5 },
630 {4'd5, 4'd6 },
631 {4'd6, 4'd7 },
632 {4'd6, 4'd8 },
633 {4'd7, 4'd9 },
634 {4'd7, 4'd10},
635 {4'd8, 4'd11},
636 {4'd9, 4'd13}: valid_cl = 1;
637 `elsif sg125
638 {4'd5, 4'd5 },
639 {4'd5, 4'd6 },
640 {4'd6, 4'd7 },
641 {4'd6, 4'd8 },
642 {4'd7, 4'd9 },
643 {4'd7, 4'd10},
644 {4'd8, 4'd11}: valid_cl = 1;
645 `elsif sg15E
646 {4'd5, 4'd5 },
647 {4'd5, 4'd6 },
648 {4'd6, 4'd7 },
649 {4'd6, 4'd8 },
650 {4'd7, 4'd9 },
651 {4'd7, 4'd10}: valid_cl = 1;
652 `elsif sg15
653 {4'd5, 4'd5 },
654 {4'd5, 4'd6 },
655 {4'd6, 4'd8 },
656 {4'd7, 4'd10}: valid_cl = 1;
657 `elsif sg187E
658 {4'd5, 4'd5 },
659 {4'd5, 4'd6 },
660 {4'd6, 4'd7 },
661 {4'd6, 4'd8 }: valid_cl = 1;
662 `elsif sg187
663 {4'd5, 4'd5 },
664 {4'd5, 4'd6 },
665 {4'd6, 4'd8 }: valid_cl = 1;
666 `elsif sg25E
667 {4'd5, 4'd5 },
668 {4'd5, 4'd6 }: valid_cl = 1;
669 `elsif sg25
670 {4'd5, 4'd5 },
671 {4'd5, 4'd6 }: valid_cl = 1;
672 `endif
673 default : valid_cl = 0;
674 endcase
675 endfunction
676
677 // find the minimum valid cas write latency
678 function [3:0] min_cwl;
679 input period;
680 real period;
681 min_cwl = (period >= 2500.0) ? 5:
682 (period >= 1875.0) ? 6:
683 (period >= 1500.0) ? 7:
684 (period >= 1250.0) ? 8:
685 (period >= 1071.0) ? 9:
686 10; // (period >= 938)
687 endfunction
688
689 // find the minimum valid cas latency
690 function [3:0] min_cl;
691 input period;
692 real period;
693 reg [3:0] cwl;
694 reg [3:0] cl;
695 begin
696 cwl = min_cwl(period);
697 for (cl=CL_MAX; cl>=CL_MIN; cl=cl-1) begin
698 if (valid_cl(cl, cwl)) begin
699 min_cl = cl;
700 end
701 end
702 end
703 endfunction