gram/simulation/runsimsoc2.sh

   1 #!/bin/bash
   2 set -e
   3
   4 LIB_DIR=./ecp5u
   5
   6 python3 simsoc.py
   7 yosys simsoc.ys
   8 cp ${LIB_DIR}/DDRDLLA.v DDRDLLA.v
   9 patch DDRDLLA.v < DDRDLLA.patch
  10 iverilog -Wall -g2012 -s simsoctb -o simsoc simsoctb.v build_simsoc/top.v dram_model/ddr3.v ${LIB_DIR}/ECLKSYNCB.v ${LIB_DIR}/EHXPLLL.v ${LIB_DIR}/PUR.v ${LIB_DIR}/GSR.v \
  11         ${LIB_DIR}/FD1S3AX.v ${LIB_DIR}/SGSR.v ${LIB_DIR}/ODDRX2F.v ${LIB_DIR}/ODDRX2DQA.v ${LIB_DIR}/DELAYF.v ${LIB_DIR}/BB.v ${LIB_DIR}/OB.v ${LIB_DIR}/IB.v \
  12         ${LIB_DIR}/DQSBUFM.v ${LIB_DIR}/UDFDL5_UDP_X.v ${LIB_DIR}/TSHX2DQSA.v ${LIB_DIR}/TSHX2DQA.v ${LIB_DIR}/ODDRX2DQSB.v ${LIB_DIR}/IDDRX2DQA.v DDRDLLA.v \
  13         ${LIB_DIR}/CLKDIVF.v
  14 vvp -n simsoc -fst-speed