gram/test/test_common.py

   1 #nmigen: UnusedElaboratable=no
   2 from nmigen import *
   3 from nmigen.hdl.ast import Past
   4
   5 from gram.common import tXXDController, tFAWController
   6 from gram.test.utils import *
   7
   8 class tXXDControllerTestCase(FHDLTestCase):
   9     def test_formal(self):
  10         def generic_test(txxd):
  11             dut = tXXDController(txxd)
  12             self.assertFormal(dut, mode="bmc", depth=txxd+1 if txxd is not None else 10)
  13
  14         generic_test(None)
  15         generic_test(0)
  16         generic_test(1)
  17         generic_test(5)
  18         generic_test(10)
  19
  20     def test_delay(self):
  21         def generic_test(txxd):
  22             dut = tXXDController(txxd)
  23
  24             yield dut.valid.eq(1)
  25             yield; yield Delay(1e-8)
  26             self.assertFalse((yield dut.ready))
  27
  28             yield dut.valid.eq(0)
  29
  30             for i in range(txxd):
  31                 self.assertFalse((yield dut.ready))
  32                 yield
  33
  34             self.assertTrue((yield dut.ready))
  35
  36             runSimulation(dut, process, "test_common_txxdcontroller.vcd")
  37
  38         generic_test(1)
  39         generic_test(5)
  40         generic_test(10)
  41
  42 class tFAWControllerTestCase(FHDLTestCase):
  43     def test_strobe_3(self):
  44         dut = tFAWController(10)
  45         def process():
  46             yield dut.valid.eq(1)
  47
  48             for i in range(3):
  49                 self.assertTrue((yield dut.ready))
  50                 yield
  51
  52             yield dut.valid.eq(0)
  53             yield
  54
  55             self.assertFalse((yield dut.valid))
  56
  57         runSimulation(dut, process, "test_common.vcd")