gram.test.test_core_bankmachine: Reduce formal test depth
[gram.git] / gram / test / test_core_bankmachine.py
1 #nmigen: UnusedElaboratable=no
2 import types, math
3
4 from nmigen import *
5 from nmigen.asserts import Assert, Assume
6
7 from gram.core.bankmachine import _AddressSlicer, BankMachine
8 from gram.test.utils import *
9
10 class AddressSlicerBijectionSpec(Elaboratable):
11 def __init__(self, dut1, dut2):
12 self.dut1 = dut1
13 self.dut2 = dut2
14
15 def elaborate(self, platform):
16 m = Module()
17 m.submodules.dut1 = dut1 = self.dut1
18 m.submodules.dut2 = dut2 = self.dut2
19
20 m.d.comb += Assert((dut1.address != dut2.address) == (Cat(dut1.row, dut1.col) != Cat(dut2.row, dut2.col)))
21 return m
22
23 class AddressSlicerTestCase(FHDLTestCase):
24 addrbits = 12
25 colbits = 5
26 address_align = 1
27
28 def test_parameters(self):
29 dut = _AddressSlicer(self.addrbits, self.colbits, self.address_align)
30 self.assertEqual(dut.col.width, self.colbits)
31 self.assertEqual(dut.address.width, self.addrbits)
32
33 def test_bijection(self):
34 dut1 = _AddressSlicer(self.addrbits, self.colbits, self.address_align)
35 dut2 = _AddressSlicer(self.addrbits, self.colbits, self.address_align)
36 spec = AddressSlicerBijectionSpec(dut1, dut2)
37 self.assertFormal(spec, "bmc", depth=1)
38
39 class BankMachineRequestGrantSpec(Elaboratable):
40 def __init__(self, dut):
41 self.dut = dut
42
43 def elaborate(self, platform):
44 m = Module()
45 m.d.comb += Assume(~dut.request_req)
46 m.d.comb += Assert(~dut.request_gnt)
47 return m
48
49 class BankMachineTestCase(FHDLTestCase):
50 settings = types.SimpleNamespace()
51 settings.cmd_buffer_depth = 1
52 settings.cmd_buffer_buffered = False
53 settings.with_auto_precharge = False
54 settings.geom = types.SimpleNamespace()
55 settings.geom.addressbits = 20
56 settings.geom.colbits = 8
57 settings.geom.rowbits = 12
58 settings.geom.bankbits = 3
59 settings.timing = types.SimpleNamespace()
60 settings.timing.tWR = 5
61 settings.timing.tCCD = 4
62 settings.timing.tRC = 6
63 settings.timing.tRAS = 7
64 settings.timing.tRP = 10
65 settings.timing.tRCD = 8
66 settings.phy = types.SimpleNamespace()
67 settings.phy.cwl = 6
68 settings.phy.nphases = 2
69
70 def test_no_request_grant(self):
71 dut = BankMachine(0, 20, 2, 1, self.settings)
72 self.assertFormal(dut, "bmc", depth=21)