gram/test/test_dfii.py

   1 from nmigen import *
   2 from lambdasoc.periph import Peripheral
   3
   4 from gram.dfii import *
   5 from gram.phy.dfi import Interface
   6 from gram.test.utils import *
   7
   8 # Phase injector CSR addresses
   9 PI_COMMAND_ADDR = 0x00
  10 PI_COMMAND_ISSUE_ADDR = 0x04
  11 PI_ADDRESS_ADDR = 0x08
  12 PI_BADDRESS_ADDR = 0x0C
  13 PI_WRDATA_ADDR = 0x10
  14 PI_RDDATA_ADDR = 0x14
  15
  16 # DFI injector CSR addresses
  17 DFII_CONTROL_ADDR = 0x00
  18
  19 class CSRHost(Peripheral, Elaboratable):
  20     def __init__(self, name="csrhost"):
  21         super().__init__(name=name)
  22         self.bank = self.csr_bank()
  23
  24     def init_bridge(self):
  25         self._bridge = self.bridge(data_width=32, granularity=8, alignment=2)
  26         self.bus = self._bridge.bus
  27
  28     def elaborate(self, platform):
  29         m = Module()
  30         m.submodules += self._bridge
  31         return m
  32
  33 class PhaseInjectorTestCase(FHDLTestCase):
  34     def generate_phaseinjector(self):
  35         dfi = Interface(12, 8, 1, 8, 1)
  36         csrhost = CSRHost()
  37         dut = PhaseInjector(csrhost.bank, dfi.phases[0])
  38         csrhost.init_bridge()
  39         m = Module()
  40         m.submodules += csrhost
  41         m.submodules += dut
  42
  43         return (m, dfi, csrhost)
  44
  45     def test_initialstate(self):
  46         m, dfi, csrhost = self.generate_phaseinjector()
  47
  48         def process():
  49             self.assertFalse((yield dfi.phases[0].cas))
  50             self.assertFalse((yield dfi.phases[0].ras))
  51             self.assertFalse((yield dfi.phases[0].we))
  52             self.assertFalse((yield dfi.phases[0].act))
  53             self.assertFalse((yield dfi.phases[0].wrdata_mask))
  54             self.assertFalse((yield dfi.phases[0].rddata_en))
  55             self.assertFalse((yield dfi.phases[0].wrdata_en))
  56
  57         runSimulation(m, process, "test_phaseinjector.vcd")
  58
  59     def test_setaddress(self):
  60         m, dfi, csrhost = self.generate_phaseinjector()
  61
  62         def process():
  63             yield from wb_write(csrhost.bus, PI_ADDRESS_ADDR >> 2, 0xCDC, sel=0xF)
  64             self.assertEqual((yield dfi.phases[0].address), 0xCDC)
  65
  66         runSimulation(m, process, "test_phaseinjector.vcd")
  67
  68     def test_setbankaddress(self):
  69         m, dfi, csrhost = self.generate_phaseinjector()
  70
  71         def process():
  72             yield from wb_write(csrhost.bus, PI_BADDRESS_ADDR >> 2, 0xA8, sel=0xF)
  73             self.assertEqual((yield dfi.phases[0].bank), 0xA8)
  74
  75         runSimulation(m, process, "test_phaseinjector.vcd")
  76
  77     def test_setwrdata(self):
  78         m, dfi, csrhost = self.generate_phaseinjector()
  79
  80         def process():
  81             yield from wb_write(csrhost.bus, PI_WRDATA_ADDR >> 2, 0xCC, sel=0xF)
  82             self.assertEqual((yield dfi.phases[0].wrdata), 0xCC)
  83
  84         runSimulation(m, process, "test_phaseinjector.vcd")
  85
  86     def test_wrdata_en(self):
  87         m, dfi, csrhost = self.generate_phaseinjector()
  88
  89         m.submodules.pc = pc = PulseCounter()
  90         m.d.comb += pc.i.eq(dfi.phases[0].wrdata_en)
  91
  92         def process():
  93             yield from wb_write(csrhost.bus, PI_COMMAND_ADDR >> 2, (1 << 4), sel=0xF)
  94             yield
  95             yield from wb_write(csrhost.bus, PI_COMMAND_ISSUE_ADDR >> 2, 1, sel=0xF)
  96             self.assertEqual((yield pc.cnt), 1)
  97             yield
  98             yield from wb_write(csrhost.bus, PI_COMMAND_ISSUE_ADDR >> 2, 1, sel=0xF)
  99             self.assertEqual((yield pc.cnt), 2)
 100
 101         runSimulation(m, process, "test_phaseinjector.vcd")
 102
 103     def test_rddata_en(self):
 104         m, dfi, csrhost = self.generate_phaseinjector()
 105
 106         m.submodules.pc = pc = PulseCounter()
 107         m.d.comb += pc.i.eq(dfi.phases[0].rddata_en)
 108
 109         def process():
 110             yield from wb_write(csrhost.bus, PI_COMMAND_ADDR >> 2, (1 << 5), sel=0xF)
 111             yield
 112             yield from wb_write(csrhost.bus, PI_COMMAND_ISSUE_ADDR >> 2, 1, sel=0xF)
 113             self.assertEqual((yield pc.cnt), 1)
 114             yield
 115             yield from wb_write(csrhost.bus, PI_COMMAND_ISSUE_ADDR >> 2, 1, sel=0xF)
 116             self.assertEqual((yield pc.cnt), 2)
 117
 118         runSimulation(m, process, "test_phaseinjector.vcd")
 119
 120 class DFIInjectorTestCase(FHDLTestCase):
 121     def generate_dfiinjector(self):
 122         csrhost = CSRHost()
 123         dut = DFIInjector(csrhost.bank, addressbits=14, bankbits=3, nranks=1, databits=16, nphases=1)
 124         csrhost.init_bridge()
 125         m = Module()
 126         m.submodules += csrhost
 127         m.submodules += dut
 128
 129         return (m, dut, csrhost)
 130
 131     def test_clk_en(self):
 132         m, dut, csrhost = self.generate_dfiinjector()
 133
 134         def process():
 135             yield from wb_write(csrhost.bus, DFII_CONTROL_ADDR >> 2, (1 << 1), sel=0xF)
 136             yield
 137             self.assertTrue((yield dut.master.phases[0].clk_en[0]))
 138
 139             yield from wb_write(csrhost.bus, DFII_CONTROL_ADDR >> 2, 0, sel=0xF)
 140             yield
 141             self.assertFalse((yield dut.master.phases[0].clk_en[0]))
 142
 143         runSimulation(m, process, "test_dfiinjector.vcd")
 144
 145     def test_odt(self):
 146         m, dut, csrhost = self.generate_dfiinjector()
 147
 148         def process():
 149             yield from wb_write(csrhost.bus, DFII_CONTROL_ADDR >> 2, (1 << 2), sel=0xF)
 150             yield
 151             self.assertTrue((yield dut.master.phases[0].odt[0]))
 152
 153             yield from wb_write(csrhost.bus, DFII_CONTROL_ADDR >> 2, 0, sel=0xF)
 154             yield
 155             self.assertFalse((yield dut.master.phases[0].odt[0]))
 156
 157         runSimulation(m, process, "test_dfiinjector.vcd")
 158
 159     def test_reset(self):
 160         m, dut, csrhost = self.generate_dfiinjector()
 161
 162         def process():
 163             yield from wb_write(csrhost.bus, DFII_CONTROL_ADDR >> 2, (1 << 3), sel=0xF)
 164             yield
 165             self.assertTrue((yield dut.master.phases[0].reset))
 166
 167             yield from wb_write(csrhost.bus, DFII_CONTROL_ADDR >> 2, 0, sel=0xF)
 168             yield
 169             self.assertFalse((yield dut.master.phases[0].reset))
 170
 171         runSimulation(m, process, "test_dfiinjector.vcd")