gram/test/test_frontend_wishbone.py

   1 #nmigen: UnusedElaboratable=no
   2
   3 from nmigen import *
   4 from lambdasoc.periph import Peripheral
   5
   6 from gram.test.utils import *
   7
   8 from gram.common import gramNativePort
   9 from gram.frontend.wishbone import gramWishbone
  10
  11 class FakeGramCrossbar:
  12     def __init__(self):
  13         self.port = gramNativePort("both", 3, 128)
  14
  15     def get_native_port(self):
  16         return self.port
  17
  18 class FakeGramCore:
  19     def __init__(self):
  20         self.crossbar = FakeGramCrossbar()
  21         self.size = 2**3*128//8
  22
  23 class GramWishboneTestCase(FHDLTestCase):
  24     def read_request(self, *, bus, native_port, adr, sel, reference_value, timeout=128, ackCallback=None):
  25         # Send a read request
  26         yield bus.adr.eq(adr)
  27         yield bus.stb.eq(1)
  28         yield bus.cyc.eq(1)
  29         yield bus.sel.eq(sel)
  30         yield bus.we.eq(0)
  31         yield
  32
  33         # Answer cmd
  34         yield native_port.cmd.ready.eq(1)
  35         yield
  36
  37         # Answer rdata
  38         yield native_port.rdata.data.eq(reference_value)
  39         yield native_port.rdata.valid.eq(1)
  40         yield
  41
  42         while not (yield bus.ack):
  43             timeout -= 1
  44             yield
  45             self.assertTrue(timeout > 0)
  46
  47         if ackCallback is not None:
  48             yield from ackCallback(bus, native_port)
  49         res = yield bus.dat_r
  50
  51         yield bus.stb.eq(0)
  52         yield bus.cyc.eq(0)
  53         yield native_port.rdata.valid.eq(0)
  54         yield
  55
  56         return res
  57
  58     def write_request(self, *, bus, native_port, adr, sel, value, timeout=128, ackCallback=None):
  59         # Send a write request
  60         yield bus.adr.eq(adr)
  61         yield bus.stb.eq(1)
  62         yield bus.cyc.eq(1)
  63         yield bus.sel.eq(sel)
  64         yield bus.we.eq(1)
  65         yield bus.dat_w.eq(value)
  66         yield
  67
  68         # Answer cmd
  69         yield native_port.cmd.ready.eq(1)
  70         yield
  71
  72         # Answer wdata
  73         yield native_port.wdata.ready.eq(1)
  74
  75         while not (yield bus.ack):
  76             timeout -= 1
  77             yield
  78             self.assertTrue(timeout > 0)
  79
  80         if ackCallback is not None:
  81             yield from ackCallback(bus, native_port)
  82         res = yield native_port.wdata.data
  83
  84         yield bus.stb.eq(0)
  85         yield bus.cyc.eq(0)
  86         yield native_port.wdata.ready.eq(0)
  87         yield
  88
  89         return res
  90
  91     def read_test(self, *, data_width, granularity):
  92         core = FakeGramCore()
  93         native_port = core.crossbar.get_native_port()
  94         dut = gramWishbone(core, data_width=data_width, granularity=granularity)
  95
  96         def process():
  97             # Initialize native port
  98             yield native_port.cmd.ready.eq(0)
  99             yield native_port.wdata.ready.eq(0)
 100             yield native_port.rdata.valid.eq(0)
 101
 102             reference_value = 0xBADDCAFE_FEEDFACE_BEEFCAFE_BAD0DAB0
 103
 104             data_granularity_radio = data_width//granularity
 105
 106             for i in range(native_port.data_width//data_width):
 107                 res = yield from self.read_request(bus=dut.bus,
 108                     native_port=native_port,
 109                     adr=i,
 110                     sel=2**data_granularity_radio-1,
 111                     reference_value=reference_value)
 112                 self.assertEqual(res, (reference_value >> (i*data_width)) & 2**data_width-1)
 113
 114         runSimulation(dut, process, "test_frontend_wishbone.vcd")
 115
 116
 117     def write_test(self, *, data_width, granularity):
 118         core = FakeGramCore()
 119         native_port = core.crossbar.get_native_port()
 120         dut = gramWishbone(core, data_width=data_width, granularity=granularity)
 121
 122         def process():
 123             # Initialize native port
 124             yield native_port.cmd.ready.eq(0)
 125             yield native_port.wdata.ready.eq(0)
 126             yield native_port.rdata.valid.eq(0)
 127
 128             reference_value = 0xBADDCAFE_FEEDFACE_BEEFCAFE_BAD0DAB0
 129
 130             data_granularity_radio = data_width//granularity
 131
 132             for i in range(native_port.data_width//data_width):
 133                 res = yield from self.write_request(bus=dut.bus,
 134                     native_port=native_port,
 135                     adr=i,
 136                     sel=2**data_granularity_radio-1,
 137                     value=(reference_value >> (i*data_width)) & 2**data_width-1)
 138                 self.assertEqual((reference_value >> (i*data_width)) & 2**data_width-1, (res >> (i*data_width)) & 2**data_width-1)
 139
 140         runSimulation(dut, process, "test_frontend_wishbone.vcd")
 141
 142     def test_init(self):
 143         core = FakeGramCore()
 144         dut = gramWishbone(core, data_width=32, granularity=8)
 145         self.assertEqual(dut.bus.data_width, 32)
 146         self.assertEqual(dut.bus.granularity, 8)
 147
 148     def test_read8_8(self):
 149         self.read_test(data_width=8, granularity=8)
 150
 151     def test_read16_8(self):
 152         self.read_test(data_width=16, granularity=8)
 153
 154     def test_read16_16(self):
 155         self.read_test(data_width=16, granularity=16)
 156
 157     def test_read32_8(self):
 158         self.read_test(data_width=32, granularity=8)
 159
 160     def test_read32_16(self):
 161         self.read_test(data_width=32, granularity=16)
 162
 163     def test_read32_32(self):
 164         self.read_test(data_width=32, granularity=32)
 165
 166     def test_read64_8(self):
 167         self.read_test(data_width=64, granularity=8)
 168
 169     def test_read64_16(self):
 170         self.read_test(data_width=64, granularity=16)
 171
 172     def test_read64_32(self):
 173         self.read_test(data_width=64, granularity=32)
 174
 175     def test_read64_64(self):
 176         self.read_test(data_width=64, granularity=64)
 177
 178     def test_write8_8(self):
 179         self.write_test(data_width=8, granularity=8)
 180
 181     def test_write16_8(self):
 182         self.write_test(data_width=16, granularity=8)
 183
 184     def test_write16_16(self):
 185         self.write_test(data_width=16, granularity=16)
 186
 187     def test_write32_8(self):
 188         self.write_test(data_width=32, granularity=8)
 189
 190     def test_write32_16(self):
 191         self.write_test(data_width=32, granularity=16)
 192
 193     def test_write32_32(self):
 194         self.write_test(data_width=32, granularity=32)
 195
 196     def test_write64_8(self):
 197         self.write_test(data_width=64, granularity=8)
 198
 199     def test_write64_16(self):
 200         self.write_test(data_width=64, granularity=16)
 201
 202     def test_write64_32(self):
 203         self.write_test(data_width=64, granularity=32)
 204
 205     def test_write64_64(self):
 206         self.write_test(data_width=64, granularity=64)
 207
 208     def test_sel_write(self):
 209         core = FakeGramCore()
 210         native_port = core.crossbar.get_native_port()
 211         dut = gramWishbone(core, data_width=32, granularity=8)
 212
 213         def process():
 214             # Initialize native port
 215             yield native_port.cmd.ready.eq(0)
 216             yield native_port.wdata.ready.eq(0)
 217             yield native_port.rdata.valid.eq(0)
 218
 219             def sel1(bus, native_port):
 220                 self.assertEqual((yield native_port.wdata.we), 0b1)
 221             def sel2(bus, native_port):
 222                 self.assertEqual((yield native_port.wdata.we), 0b10)
 223             def sel3(bus, native_port):
 224                 self.assertEqual((yield native_port.wdata.we), 0b100)
 225             def sel4(bus, native_port):
 226                 self.assertEqual((yield native_port.wdata.we), 0b1000)
 227             def sel5(bus, native_port):
 228                 self.assertEqual((yield native_port.wdata.we), 0b10000)
 229             def sel9(bus, native_port):
 230                 self.assertEqual((yield native_port.wdata.we), 0b100000000)
 231             def sel13(bus, native_port):
 232                 self.assertEqual((yield native_port.wdata.we), 0b1000000000000)
 233             def selfirstdword(bus, native_port):
 234                 self.assertEqual((yield native_port.wdata.we), 0xF)
 235             def sellastdword(bus, native_port):
 236                 self.assertEqual((yield native_port.wdata.we), 0xF000)
 237
 238             yield from self.write_request(bus=dut.bus,
 239                 native_port=native_port,
 240                 adr=0,
 241                 sel=1,
 242                 value=0xCA,
 243                 timeout=128,
 244                 ackCallback=sel1)
 245
 246             yield from self.write_request(bus=dut.bus,
 247                 native_port=native_port,
 248                 adr=0,
 249                 sel=0b10,
 250                 value=0xCA,
 251                 timeout=128,
 252                 ackCallback=sel2)
 253
 254             yield from self.write_request(bus=dut.bus,
 255                 native_port=native_port,
 256                 adr=0,
 257                 sel=0b100,
 258                 value=0xCA,
 259                 timeout=128,
 260                 ackCallback=sel3)
 261
 262             yield from self.write_request(bus=dut.bus,
 263                 native_port=native_port,
 264                 adr=0,
 265                 sel=0b1000,
 266                 value=0xCA,
 267                 timeout=128,
 268                 ackCallback=sel4)
 269
 270             yield from self.write_request(bus=dut.bus,
 271                 native_port=native_port,
 272                 adr=1,
 273                 sel=1,
 274                 value=0xCA,
 275                 timeout=128,
 276                 ackCallback=sel5)
 277
 278         yield from self.write_request(bus=dut.bus,
 279                 native_port=native_port,
 280                 adr=2,
 281                 sel=1,
 282                 value=0xCA,
 283                 timeout=128,
 284                 ackCallback=sel9)
 285
 286         yield from self.write_request(bus=dut.bus,
 287                 native_port=native_port,
 288                 adr=3,
 289                 sel=1,
 290                 value=0xCA,
 291                 timeout=128,
 292                 ackCallback=sel13)
 293
 294         yield from self.write_request(bus=dut.bus,
 295                 native_port=native_port,
 296                 adr=3,
 297                 sel=0xF,
 298                 value=0xCA,
 299                 timeout=128,
 300                 ackCallback=sellastdword)
 301
 302         yield from self.write_request(bus=dut.bus,
 303                 native_port=native_port,
 304                 adr=4,
 305                 sel=0xF,
 306                 value=0xCA,
 307                 timeout=128,
 308                 ackCallback=selfirstdword)
 309
 310         runSimulation(dut, process, "test_frontend_wishbone.vcd")
 311
 312     def test_sel_empty(self):
 313         core = FakeGramCore()
 314         native_port = core.crossbar.get_native_port()
 315         dut = gramWishbone(core, data_width=32, granularity=8)
 316
 317         def process():
 318             # Initialize native port
 319             yield native_port.cmd.ready.eq(0)
 320             yield native_port.wdata.ready.eq(0)
 321             yield native_port.rdata.valid.eq(0)
 322
 323             def selfirstdword(bus, native_port):
 324                 self.assertEqual((yield native_port.wdata.we), 0xF)
 325
 326             yield from self.write_request(bus=dut.bus,
 327                 native_port=native_port,
 328                 adr=0,
 329                 sel=0,
 330                 value=0xAAAAAAAA,
 331                 timeout=128,
 332                 ackCallback=selfirstdword)
 333
 334         runSimulation(dut, process, "test_frontend_wishbone.vcd")