gram/test/test_phy_ecp5ddrphy.py

   1 from nmigen import *
   2
   3 from gram.phy.ecp5ddrphy import _DQSBUFMSettingManager
   4 from gram.test.utils import *
   5
   6 class DQSBUFMSettingManagerTestCase(FHDLTestCase):
   7     class MockCSR:
   8         def __init__(self):
   9             self.w_stb = Signal()
  10             self.w_data = Signal(3)
  11
  12     def test_pause_timing(self):
  13         csr = self.MockCSR()
  14         dut = _DQSBUFMSettingManager(csr)
  15
  16         def process():
  17             self.assertFalse((yield dut.pause))
  18
  19             yield csr.w_stb.eq(1)
  20             yield
  21             yield csr.w_stb.eq(0)
  22             yield
  23
  24             self.assertTrue((yield dut.pause))
  25             yield
  26             self.assertTrue((yield dut.pause))
  27             yield
  28             self.assertFalse((yield dut.pause))
  29
  30         runSimulation(dut, process, "test_phy_ecp5ddrphy.vcd")
  31
  32     def test_value(self):
  33         csr = self.MockCSR()
  34         dut = _DQSBUFMSettingManager(csr)
  35
  36         def process():
  37             # Check default value
  38             self.assertEqual((yield dut.readclksel), 0)
  39
  40             yield csr.w_data.eq(0b101)
  41             yield csr.w_stb.eq(1)
  42             yield
  43             yield csr.w_stb.eq(0)
  44             yield
  45
  46             # Ensure value isn't being changed at that point
  47             self.assertEqual((yield dut.readclksel), 0)
  48             yield; yield Delay(1e-9)
  49
  50             # Ensure value is changed after the second clock cycle
  51             self.assertEqual((yield dut.readclksel), 0b101)
  52
  53         runSimulation(dut, process, "test_phy_ecp5ddrphy.vcd")