hwacha/decode_hwacha.h

   1 #ifndef _DECODE_HWACHA_H
   2 #define _DECODE_HWACHA_H
   3
   4 #define XS1 (xs1)
   5 #define XS2 (xs2)
   6 #define WRITE_XRD(value) (xd = value)
   7
   8 #define NXPR (h->get_ct_state()->nxpr)
   9 #define NFPR (h->get_ct_state()->nfpr)
  10 #define MAXVL (h->get_ct_state()->maxvl)
  11 #define VL (h->get_ct_state()->vl)
  12 #define WRITE_NXPR(nxprnext) (h->get_ct_state()->nxpr = (nxprnext))
  13 #define WRITE_NFPR(nfprnext) (h->get_ct_state()->nfpr = (nfprnext))
  14 #define WRITE_MAXVL(maxvlnext) (h->get_ct_state()->maxvl = (maxvlnext))
  15 #define WRITE_VL(vlnext) (h->get_ct_state()->vl = (vlnext))
  16
  17 #define INSN_RS1 (insn.rs1())
  18 #define INSN_RS2 (insn.rs2())
  19 #define INSN_RS3 (insn.rs3())
  20 #define INSN_RD (insn.rd())
  21 #define INSN_SEG ((insn.i_imm() >> 9)+1)
  22
  23 #define UT_READ_XPR(idx, src) (h->get_ut_state(idx)->XPR[src])
  24 #define UT_WRITE_XPR(idx, dst, value) (h->get_ut_state(idx)->XPR.write(dst, value))
  25 #define UT_RS1(idx) (UT_READ_XPR(idx, INSN_RS1))
  26 #define UT_RS2(idx) (UT_READ_XPR(idx, INSN_RS2))
  27 #define UT_WRITE_RD(idx, value) (UT_WRITE_XPR(idx, INSN_RD, value))
  28
  29 #define UT_READ_FPR(idx, src) (h->get_ut_state(idx)->FPR[src])
  30 #define UT_WRITE_FPR(idx, dst, value) (h->get_ut_state(idx)->FPR.write(dst, value))
  31 #define UT_FRS1(idx) (UT_READ_FPR(idx, INSN_RS1))
  32 #define UT_FRS2(idx) (UT_READ_FPR(idx, INSN_RS2))
  33 #define UT_FRS3(idx) (UT_READ_FPR(idx, INSN_RS3))
  34 #define UT_WRITE_FRD(idx, value) (UT_WRITE_FPR(idx, INSN_RD, value))
  35
  36 #define VEC_SEG_LOAD(dst, func, inc) \
  37   VEC_SEG_ST_LOAD(dst, func, INSN_SEG*inc, inc)
  38
  39 #define VEC_SEG_ST_LOAD(dst, func, stride, inc) \
  40   reg_t seg_addr = XS1; \
  41   for (uint32_t i=0; i<VL; i++) { \
  42     reg_t addr = seg_addr; \
  43     seg_addr += stride; \
  44     for (uint32_t j=0; j<INSN_SEG; j++) { \
  45       UT_WRITE_##dst(i, INSN_RD+j, p->get_mmu()->func(addr)); \
  46       addr += inc; \
  47     } \
  48   }
  49
  50 #define VEC_SEG_STORE(src, func, inc) \
  51   VEC_SEG_ST_STORE(src, func, INSN_SEG*inc, inc)
  52
  53 #define VEC_SEG_ST_STORE(src, func, stride, inc) \
  54   reg_t seg_addr = XS1; \
  55   for (uint32_t i=0; i<VL; i++) { \
  56     reg_t addr = seg_addr; \
  57     seg_addr += stride; \
  58     for (uint32_t j=0; j<INSN_SEG; j++) { \
  59       p->get_mmu()->func(addr, UT_READ_##src(i, INSN_RD+j)); \
  60       addr += inc; \
  61     } \
  62   }
  63
  64 #endif