+ # Add subproject to our running list
+
+ subprojects="$subprojects hwacha"
+
+ # Process the subproject appropriately. If enabled add it to the
+ # $enabled_subprojects running shell variable, set a
+ # SUBPROJECT_ENABLED C define, and include the appropriate
+ # 'subproject.ac'.
+
+
+ { $as_echo "$as_me:${as_lineno-$LINENO}: configuring default subproject : hwacha" >&5
+$as_echo "$as_me: configuring default subproject : hwacha" >&6;}
+ ac_config_files="$ac_config_files hwacha.mk:hwacha/hwacha.mk.in"
+
+ enable_hwacha_sproj="yes"
+ subprojects_enabled="$subprojects_enabled hwacha"
+
+$as_echo "#define HWACHA_ENABLED /**/" >>confdefs.h
+
+
+
+
+
+
+ # Determine if this is a required or an optional subproject
+
+
+
+ # Determine if there is a group with the same name
+
+
+
+ # Create variations of the subproject name suitable for use as a CPP
+ # enabled define, a shell enabled variable, and a shell function
+
+
+
+
+
+
+
+
+
+
+
# Add subproject to our running list
subprojects="$subprojects softfloat"
do
case $ac_config_target in
"riscv.mk") CONFIG_FILES="$CONFIG_FILES riscv.mk:riscv/riscv.mk.in" ;;
+ "hwacha.mk") CONFIG_FILES="$CONFIG_FILES hwacha.mk:hwacha/hwacha.mk.in" ;;
"softfloat.mk") CONFIG_FILES="$CONFIG_FILES softfloat.mk:softfloat/softfloat.mk.in" ;;
"softfloat_riscv.mk") CONFIG_FILES="$CONFIG_FILES softfloat_riscv.mk:softfloat_riscv/softfloat_riscv.mk.in" ;;
"config.h") CONFIG_HEADERS="$CONFIG_HEADERS config.h" ;;
# The '*' suffix indicates an optional subproject. The '**' suffix
# indicates an optional subproject which is also the name of a group.
-MCPPBS_SUBPROJECTS([ riscv, softfloat, softfloat_riscv ])
+MCPPBS_SUBPROJECTS([ riscv, hwacha, softfloat, softfloat_riscv ])
#-------------------------------------------------------------------------
# MCPPBS subproject groups
This directory contains work in progress on Hwacha, a data-parallel
-accelerator. It is not currently usable.
+accelerator.
--- /dev/null
+#ifndef _DECODE_HWACHA_H
+#define _DECODE_HWACHA_H
+
+#define XS1 (xs1)
+#define XS2 (xs2)
+#define WRITE_XRD(value) (xd = value)
+
+#define NXPR (h->get_ct_state()->nxpr)
+#define NFPR (h->get_ct_state()->nfpr)
+#define MAXVL (h->get_ct_state()->maxvl)
+#define VL (h->get_ct_state()->vl)
+#define WRITE_NXPR(nxprnext) (h->get_ct_state()->nxpr = (nxprnext))
+#define WRITE_NFPR(nfprnext) (h->get_ct_state()->nfpr = (nfprnext))
+#define WRITE_MAXVL(maxvlnext) (h->get_ct_state()->maxvl = (maxvlnext))
+#define WRITE_VL(vlnext) (h->get_ct_state()->vl = (vlnext))
+
+#define INSN_RS1 (insn.rs1())
+#define INSN_RS2 (insn.rs2())
+#define INSN_RS3 (insn.rs3())
+#define INSN_RD (insn.rd())
+#define INSN_SEG ((insn.i_imm() >> 9)+1)
+
+#define UT_READ_XPR(idx, src) (h->get_ut_state(idx)->XPR[src])
+#define UT_WRITE_XPR(idx, dst, value) (h->get_ut_state(idx)->XPR.write(dst, value))
+#define UT_RS1(idx) (UT_READ_XPR(idx, INSN_RS1))
+#define UT_RS2(idx) (UT_READ_XPR(idx, INSN_RS2))
+#define UT_WRITE_RD(idx, value) (UT_WRITE_XPR(idx, INSN_RD, value))
+
+#define UT_READ_FPR(idx, src) (h->get_ut_state(idx)->FPR[src])
+#define UT_WRITE_FPR(idx, dst, value) (h->get_ut_state(idx)->FPR.write(dst, value))
+#define UT_FRS1(idx) (UT_READ_FPR(idx, INSN_RS1))
+#define UT_FRS2(idx) (UT_READ_FPR(idx, INSN_RS2))
+#define UT_FRS3(idx) (UT_READ_FPR(idx, INSN_RS3))
+#define UT_WRITE_FRD(idx, value) (UT_WRITE_FPR(idx, INSN_RD, value))
+
+#define VEC_SEG_LOAD(dst, func, inc) \
+ VEC_SEG_ST_LOAD(dst, func, INSN_SEG*inc, inc)
+
+#define VEC_SEG_ST_LOAD(dst, func, stride, inc) \
+ reg_t seg_addr = XS1; \
+ for (uint32_t i=0; i<VL; i++) { \
+ reg_t addr = seg_addr; \
+ seg_addr += stride; \
+ for (uint32_t j=0; j<INSN_SEG; j++) { \
+ UT_WRITE_##dst(i, INSN_RD+j, p->get_mmu()->func(addr)); \
+ addr += inc; \
+ } \
+ }
+
+#define VEC_SEG_STORE(src, func, inc) \
+ VEC_SEG_ST_STORE(src, func, INSN_SEG*inc, inc)
+
+#define VEC_SEG_ST_STORE(src, func, stride, inc) \
+ reg_t seg_addr = XS1; \
+ for (uint32_t i=0; i<VL; i++) { \
+ reg_t addr = seg_addr; \
+ seg_addr += stride; \
+ for (uint32_t j=0; j<INSN_SEG; j++) { \
+ p->get_mmu()->func(addr, UT_READ_##src(i, INSN_RD+j)); \
+ addr += inc; \
+ } \
+ }
+
+#endif
--- /dev/null
+#ifndef _DECODE_HWACHA_UT_H
+#define _DECODE_HWACHA_UT_H
+
+#include "decode_hwacha.h"
+
+#define UTIDX (i)
+
+#undef RS1
+#undef RS2
+#undef WRITE_RD
+
+#define RS1 UT_RS1(UTIDX)
+#define RS2 UT_RS2(UTIDX)
+#define WRITE_RD(value) UT_WRITE_RD(UTIDX, value)
+
+#undef FRS1
+#undef FRS2
+#undef FRS3
+#undef WRITE_FRD
+
+#define FRS1 UT_FRS1(UTIDX)
+#define FRS2 UT_FRS2(UTIDX)
+#define FRS3 UT_FRS3(UTIDX)
+#define WRITE_FRD(value) UT_WRITE_FRD(UTIDX, value)
+
+// we assume the vector unit has floating-point alus
+#undef require_fp
+#define require_fp
+
+// YUNSUP FIXME
+#undef set_fp_exceptions
+#define set_fp_exceptions
+
+#endif
+++ /dev/null
-hwacha_disassembler::hwacha_disassembler()
-{
- #define DEFINE_RS1(code) DISASM_INSN(#code, code, 0, xrs1_reg)
- #define DEFINE_RS1_RS2(code) DISASM_INSN(#code, code, 0, xrs1_reg, xrs2_reg)
- #define DEFINE_VEC_XMEM(code) DISASM_INSN(#code, code, 0, vxrd_reg, xrs1_reg)
- #define DEFINE_VEC_XMEMST(code) DISASM_INSN(#code, code, 0, vxrd_reg, xrs1_reg, xrs2_reg)
- #define DEFINE_VEC_FMEM(code) DISASM_INSN(#code, code, 0, vfrd_reg, xrs1_reg)
- #define DEFINE_VEC_FMEMST(code) DISASM_INSN(#code, code, 0, vfrd_reg, xrs1_reg, xrs2_reg)
-
- DEFINE_RS1(vxcptsave);
- DEFINE_RS1(vxcptrestore);
- DEFINE_NOARG(vxcptkill);
-
- DEFINE_RS1(vxcptevac);
- DEFINE_NOARG(vxcpthold);
- DEFINE_RS1_RS2(venqcmd);
- DEFINE_RS1_RS2(venqimm1);
- DEFINE_RS1_RS2(venqimm2);
- DEFINE_RS1_RS2(venqcnt);
-
- DEFINE_VEC_XMEM(vld);
- DEFINE_VEC_XMEM(vlw);
- DEFINE_VEC_XMEM(vlwu);
- DEFINE_VEC_XMEM(vlh);
- DEFINE_VEC_XMEM(vlhu);
- DEFINE_VEC_XMEM(vlb);
- DEFINE_VEC_XMEM(vlbu);
- DEFINE_VEC_FMEM(vfld);
- DEFINE_VEC_FMEM(vflw);
- DEFINE_VEC_XMEMST(vlstd);
- DEFINE_VEC_XMEMST(vlstw);
- DEFINE_VEC_XMEMST(vlstwu);
- DEFINE_VEC_XMEMST(vlsth);
- DEFINE_VEC_XMEMST(vlsthu);
- DEFINE_VEC_XMEMST(vlstb);
- DEFINE_VEC_XMEMST(vlstbu);
- DEFINE_VEC_FMEMST(vflstd);
- DEFINE_VEC_FMEMST(vflstw);
-
- DEFINE_VEC_XMEM(vsd);
- DEFINE_VEC_XMEM(vsw);
- DEFINE_VEC_XMEM(vsh);
- DEFINE_VEC_XMEM(vsb);
- DEFINE_VEC_FMEM(vfsd);
- DEFINE_VEC_FMEM(vfsw);
- DEFINE_VEC_XMEMST(vsstd);
- DEFINE_VEC_XMEMST(vsstw);
- DEFINE_VEC_XMEMST(vssth);
- DEFINE_VEC_XMEMST(vsstb);
- DEFINE_VEC_FMEMST(vfsstd);
- DEFINE_VEC_FMEMST(vfsstw);
-
- DISASM_INSN("vmvv", vmvv, 0, vxrd_reg, vxrs1_reg);
- DISASM_INSN("vmsv", vmsv, 0, vxrd_reg, xrs1_reg);
- DISASM_INSN("vmst", vmst, 0, vxrd_reg, xrs1_reg, xrs2_reg);
- DISASM_INSN("vmts", vmts, 0, xrd_reg, vxrs1_reg, xrs2_reg);
- DISASM_INSN("vfmvv", vfmvv, 0, vfrd_reg, vfrs1_reg);
- DISASM_INSN("vfmsv", vfmsv, 0, vfrd_reg, frs1_reg);
- DISASM_INSN("vfmst", vfmst, 0, vfrd_reg, frs1_reg, frs2_reg);
- DISASM_INSN("vfmts", vfmts, 0, frd_reg, vfrs1_reg, frs2_reg);
-
- DEFINE_RS1_RS2(vvcfg);
- DEFINE_RS1_RS2(vtcfg);
-
- DISASM_INSN("vvcfgivl", vvcfgivl, 0, xrd_reg, xrs1_reg, nxregs_reg, nfregs_reg);
- DISASM_INSN("vtcfgivl", vtcfgivl, 0, xrd_reg, xrs1_reg, nxregs_reg, nfregs_reg);
- DISASM_INSN("vsetvl", vsetvl, 0, xrd_reg, xrs1_reg);
- DISASM_INSN("vf", vf, 0, xrs1_reg, imm);
-
- DEFINE_NOARG(fence_v_l);
- DEFINE_NOARG(fence_v_g);
-}
--- /dev/null
+#include "hwacha.h"
+
+void ct_state_t::reset()
+{
+ vl = 0;
+ maxvl = 32;
+ nxpr = 32;
+ nfpr = 32;
+
+ vf_pc = -1;
+}
+
+void ut_state_t::reset()
+{
+ run = false;
+ XPR.reset();
+ FPR.reset();
+}
+
+hwacha_t::hwacha_t()
+{
+ ct_state.reset();
+ for (int i=0; i<max_uts; i++)
+ ut_state[i].reset();
+}
+
+std::vector<insn_desc_t> hwacha_t::get_instructions()
+{
+ std::vector<insn_desc_t> insns;
+ #define DECLARE_INSN(name, match, mask) \
+ extern reg_t hwacha_##name(processor_t*, insn_t, reg_t); \
+ insns.push_back((insn_desc_t){match, mask, &::illegal_instruction, hwacha_##name});
+ #include "opcodes_hwacha.h"
+ #undef DECLARE_INSN
+ return insns;
+}
+
+bool hwacha_t::vf_active()
+{
+ for (int i=0; i<get_ct_state()->vl; i++) {
+ if (get_ut_state(i)->run)
+ return true;
+ }
+
+ return false;
+}
#ifndef _HWACHA_H
#define _HWACHA_H
-// vector stuff
-#define VL vl
-
-#define UT_RS1(idx) uts[idx]->XPR[insn.rtype.rs1]
-#define UT_RS2(idx) uts[idx]->XPR[insn.rtype.rs2]
-#define UT_RD(idx) uts[idx]->XPR.write_port(insn.rtype.rd)
-#define UT_RA(idx) uts[idx]->XPR.write_port(1)
-#define UT_FRS1(idx) uts[idx]->FPR[insn.ftype.rs1]
-#define UT_FRS2(idx) uts[idx]->FPR[insn.ftype.rs2]
-#define UT_FRS3(idx) uts[idx]->FPR[insn.ftype.rs3]
-#define UT_FRD(idx) uts[idx]->FPR.write_port(insn.ftype.rd)
-#define UT_RM(idx) ((insn.ftype.rm != 7) ? insn.ftype.rm : \
- ((uts[idx]->fsr & FSR_RD) >> FSR_RD_SHIFT))
-
-#define UT_LOOP_START for (int i=0;i<VL; i++) {
-#define UT_LOOP_END }
-#define UT_LOOP_RS1 UT_RS1(i)
-#define UT_LOOP_RS2 UT_RS2(i)
-#define UT_LOOP_RD UT_RD(i)
-#define UT_LOOP_RA UT_RA(i)
-#define UT_LOOP_FRS1 UT_FRS1(i)
-#define UT_LOOP_FRS2 UT_FRS2(i)
-#define UT_LOOP_FRS3 UT_FRS3(i)
-#define UT_LOOP_FRD UT_FRD(i)
-#define UT_LOOP_RM UT_RM(i)
-
-#define VEC_LOAD(dst, func, inc) \
- reg_t addr = RS1; \
- UT_LOOP_START \
- UT_LOOP_##dst = mmu.func(addr); \
- addr += inc; \
- UT_LOOP_END
-
-#define VEC_STORE(src, func, inc) \
- reg_t addr = RS1; \
- UT_LOOP_START \
- mmu.func(addr, UT_LOOP_##src); \
- addr += inc; \
- UT_LOOP_END
-
-enum vt_command_t
+#include "extension.h"
+
+struct ct_state_t
+{
+ void reset();
+
+ uint32_t nxpr;
+ uint32_t nfpr;
+ uint32_t maxvl;
+ uint32_t vl;
+
+ reg_t vf_pc;
+};
+
+struct ut_state_t
{
- vt_command_stop,
+ void reset();
+
+ bool run;
+ regfile_t<reg_t, 32, true> XPR;
+ regfile_t<reg_t, 32, false> FPR;
+};
+
+class hwacha_t : public extension_t
+{
+public:
+ hwacha_t();
+ const char* name() { return "hwacha"; }
+ std::vector<insn_desc_t> get_instructions();
+ ct_state_t* get_ct_state() { return &ct_state; }
+ ut_state_t* get_ut_state(int idx) { return &ut_state[idx]; }
+ bool vf_active();
+
+private:
+ static const int max_uts = 2048;
+ ct_state_t ct_state;
+ ut_state_t ut_state[max_uts];
};
+REGISTER_EXTENSION(hwacha, []() { return new hwacha_t; })
+
#endif
--- /dev/null
+get_insn_list = $(shell cat $(1) | sed 's/DECLARE_INSN(\(.*\),.*,.*)/\1/')
+get_opcode = $(shell grep \\\<$(2)\\\> $(1) | sed 's/DECLARE_INSN(.*,\(.*\),.*)/\1/')
+
+hwacha_subproject_deps = \
+ riscv \
+ softfloat \
+
+hwacha_install_prog_srcs = \
+
+hwacha_hdrs = \
+ hwacha.h \
+ decode_hwacha.h \
+ decode_hwacha_ut.h \
+ opcodes_hwacha.h \
+ opcodes_hwacha_ut.h \
+
+hwacha_srcs = \
+ hwacha.cc \
+ $(hwacha_gen_srcs) \
+ $(hwacha_ut_gen_srcs) \
+
+hwacha_test_srcs =
+
+hwacha_gen_srcs = \
+ $(addsuffix .cc, $(call get_insn_list,$(src_dir)/hwacha/opcodes_hwacha.h))
+
+$(hwacha_gen_srcs): %.cc: insns/%.h insn_template_hwacha.cc
+ sed 's/NAME/$(subst .cc,,$@)/' $(src_dir)/hwacha/insn_template_hwacha.cc | sed 's/OPCODE/$(call get_opcode,$(src_dir)/hwacha/opcodes_hwacha.h,$(subst .cc,,$@))/' > $@
+
+hwacha_ut_gen_srcs = \
+ $(addsuffix .cc, $(call get_insn_list,$(src_dir)/hwacha/opcodes_hwacha_ut.h))
+
+$(hwacha_ut_gen_srcs): %.cc: insns_ut/%.h insn_template_hwacha_ut.cc
+ sed 's/NAME/$(subst .cc,,$@)/' $(src_dir)/hwacha/insn_template_hwacha_ut.cc | sed 's/OPCODE/$(call get_opcode,$(src_dir)/hwacha/opcodes_hwacha_ut.h,$(subst .cc,,$@))/' > $@
+
--- /dev/null
+// See LICENSE for license details.
+
+#include "config.h"
+#include "processor.h"
+#include "mmu.h"
+#include "hwacha.h"
+#include "decode_hwacha.h"
+#include "rocc.h"
+#include <assert.h>
+
+reg_t hwacha_NAME(processor_t* p, insn_t insn, reg_t pc)
+{
+ int xprlen = 64;
+ reg_t npc = sext_xprlen(pc + insn_length(OPCODE));
+ hwacha_t* h = static_cast<hwacha_t*>(p->get_extension());
+ rocc_insn_union_t u;
+ u.i = insn;
+ reg_t xs1 = u.r.xs1 ? RS1 : -1;
+ reg_t xs2 = u.r.xs2 ? RS2 : -1;
+ reg_t xd = -1;
+ #include "insns/NAME.h"
+ if (u.r.xd) WRITE_RD(xd);
+ return npc;
+}
--- /dev/null
+// See LICENSE for license details.
+
+#include "config.h"
+#include "processor.h"
+#include "mmu.h"
+#include "softfloat.h"
+#include "platform.h" // softfloat isNaNF32UI, etc.
+#include "internals.h" // ditto
+#include "hwacha.h"
+#include "decode_hwacha_ut.h"
+#include <assert.h>
+
+reg_t hwacha_NAME(processor_t* p, insn_t insn, reg_t pc)
+{
+ int xprlen = 64;
+ reg_t npc = sext_xprlen(pc + insn_length(OPCODE));
+ hwacha_t* h = static_cast<hwacha_t*>(p->get_extension());
+ for (uint32_t i=0; i<VL; i++) {
+ #include "insns_ut/NAME.h"
+ }
+ return npc;
+}
+++ /dev/null
-require_vector;
-if (RS1 & 0x1) FRD = FRS2;
+++ /dev/null
-require_vector;
-if (~RS1 & 0x1) FRD = FRS2;
+++ /dev/null
-require_vector;
-if (RS1 & 0x1) RD = RS2;
+++ /dev/null
-require_vector;
-if (~RS1 & 0x1) RD = RS2;
+++ /dev/null
-require_vector;
-utmode = false;
-throw vt_command_stop;
+++ /dev/null
-require_vector;
-RD = utidx;
-require_vector;
-for (int i=0; i<VL; i++)
-{
- uts[i]->pc = ITYPE_EADDR;
- uts[i]->utmode = true;
- uts[i]->run = true;
- while (uts[i]->utmode)
- uts[i]->step(100, false); // XXX
+if (VL) {
+ if (!h->vf_active()) {
+ h->get_ct_state()->vf_pc = XS1 + insn.s_imm();
+ for (uint32_t i=0; i<VL; i++)
+ h->get_ut_state(i)->run = true;
+ }
+
+ mmu_t::insn_fetch_t ut_fetch = p->get_mmu()->load_insn(h->get_ct_state()->vf_pc);
+ insn_t ut_insn = ut_fetch.insn.insn;
+
+ bool matched = false;
+
+ #define DECLARE_INSN(name, match, mask) \
+ extern reg_t hwacha_##name(processor_t*, insn_t, reg_t); \
+ if ((ut_insn.bits() & mask) == match) { \
+ h->get_ct_state()->vf_pc = hwacha_##name(p, ut_insn, h->get_ct_state()->vf_pc); \
+ matched = true; \
+ }
+ #include "opcodes_hwacha_ut.h"
+ #undef DECLARE_INSN
+
+ // YUNSUP FIXME
+ assert(matched);
+
+ // if vf is still running, rewind pc so that it will execute again
+ if (h->vf_active())
+ npc = pc;
}
+++ /dev/null
-require_vector;
-require_fp;
-VEC_LOAD(FRD, load_int64, 8);
+VEC_SEG_LOAD(FPR, load_int64, 8);
+VEC_SEG_ST_LOAD(FPR, load_int64, XS2, 8);
+VEC_SEG_ST_LOAD(FPR, load_int32, XS2, 4);
+VEC_SEG_LOAD(FPR, load_int32, 4);
+++ /dev/null
-require_vector;
-require_fp;
-VEC_LOAD(FRD, load_int64, RS2);
+++ /dev/null
-require_vector;
-require_fp;
-VEC_LOAD(FRD, load_int32, RS2);
+++ /dev/null
-require_vector;
-require_fp;
-VEC_LOAD(FRD, load_int32, 4);
+++ /dev/null
-require_vector;
-require_fp;
-assert(0 <= RS2 && RS2 < MAX_UTS);
-UT_FRD(RS2) = FRS1;
+++ /dev/null
-require_vector;
-require_fp;
-UT_LOOP_START
- UT_LOOP_FRD = FRS1;
-UT_LOOP_END
+++ /dev/null
-require_vector;
-require_fp;
-assert(0 <= RS2 && RS2 < MAX_UTS);
-FRD = UT_FRS1(RS2);
+++ /dev/null
-require_vector;
-require_fp;
-UT_LOOP_START
- UT_LOOP_FRD = UT_LOOP_FRS1;
-UT_LOOP_END
+++ /dev/null
-require_vector;
-require_fp;
-VEC_STORE(FRD, store_uint64, 8);
+VEC_SEG_STORE(FPR, store_uint64, 8);
+VEC_SEG_ST_STORE(FPR, store_uint64, XS2, 8);
+VEC_SEG_ST_STORE(FPR, store_uint32, XS2, 4);
+VEC_SEG_STORE(FPR, store_uint32, 4);
+++ /dev/null
-require_vector;
-require_fp;
-VEC_STORE(FRD, store_uint64, RS2);
+++ /dev/null
-require_vector;
-require_fp;
-VEC_STORE(FRD, store_uint32, RS2);
+++ /dev/null
-require_vector;
-require_fp;
-VEC_STORE(FRD, store_uint32, 4);
--- /dev/null
+WRITE_XRD((NXPR & 0x3f) | ((NFPR & 0x3f) << 6));
--- /dev/null
+WRITE_XRD(VL);
+++ /dev/null
-require_vector;
-VEC_LOAD(RD, load_int8, 1);
+++ /dev/null
-require_vector;
-VEC_LOAD(RD, load_uint8, 1);
+++ /dev/null
-require_vector;
-require_xpr64;
-VEC_LOAD(RD, load_int64, 8);
+++ /dev/null
-require_vector;
-VEC_LOAD(RD, load_int16, 2);
+++ /dev/null
-require_vector;
-VEC_LOAD(RD, load_uint16, 2);
+VEC_SEG_LOAD(XPR, load_int8, 1);
+VEC_SEG_LOAD(XPR, load_uint8, 1);
+VEC_SEG_LOAD(XPR, load_int64, 8);
+VEC_SEG_LOAD(XPR, load_int16, 2);
+VEC_SEG_LOAD(XPR, load_uint16, 2);
+VEC_SEG_ST_LOAD(XPR, load_int8, XS2, 1);
+VEC_SEG_ST_LOAD(XPR, load_uint8, XS2, 1);
+VEC_SEG_ST_LOAD(XPR, load_int64, XS2, 8);
+VEC_SEG_ST_LOAD(XPR, load_int16, XS2, 2);
+VEC_SEG_ST_LOAD(XPR, load_uint16, XS2, 2);
+VEC_SEG_ST_LOAD(XPR, load_int32, XS2, 4);
+VEC_SEG_ST_LOAD(XPR, load_uint32, XS2, 4);
+VEC_SEG_LOAD(XPR, load_int32, 4);
+VEC_SEG_LOAD(XPR, load_uint32, 4);
+++ /dev/null
-require_vector;
-VEC_LOAD(RD, load_int8, RS2);
+++ /dev/null
-require_vector;
-VEC_LOAD(RD, load_uint8, RS2);
+++ /dev/null
-require_vector;
-require_xpr64;
-VEC_LOAD(RD, load_int64, RS2);
+++ /dev/null
-require_vector;
-VEC_LOAD(RD, load_int16, RS2);
+++ /dev/null
-require_vector;
-VEC_LOAD(RD, load_uint16, RS2);
+++ /dev/null
-require_vector;
-VEC_LOAD(RD, load_int32, RS2);
+++ /dev/null
-require_vector;
-VEC_LOAD(RD, load_uint32, RS2);
+++ /dev/null
-require_vector;
-VEC_LOAD(RD, load_int32, 4);
+++ /dev/null
-require_vector;
-VEC_LOAD(RD, load_uint32, 4);
+++ /dev/null
-require_vector;
-assert(0 <= RS2 && RS2 < MAX_UTS);
-UT_RD(RS2) = RS1;
-require_vector;
-UT_LOOP_START
- UT_LOOP_RD = RS1;
-UT_LOOP_END
+for (uint32_t i=0; i<VL; i++)
+ UT_WRITE_RD(i, XS1);
+++ /dev/null
-require_vector;
-assert(0 <= RS2 && RS2 < MAX_UTS);
-RD = UT_RS1(RS2);
-require_vector;
-UT_LOOP_START
- UT_LOOP_RD = UT_LOOP_RS1;
-UT_LOOP_END
+for (uint32_t i=0; i<VL; i++) {
+ UT_WRITE_RD(i, UT_RS1(i));
+}
+++ /dev/null
-require_vector;
-VEC_STORE(RD, store_uint8, 1);
+++ /dev/null
-require_vector;
-require_xpr64;
-VEC_STORE(RD, store_uint64, 8);
--- /dev/null
+uint32_t nxpr = (XS1 & 0x3f) + (insn.i_imm() & 0x3f);
+uint32_t nfpr = ((XS1 >> 6) & 0x3f) + ((insn.i_imm() >> 6) & 0x3f);
+// YUNSUP FIXME
+// raise trap when nxpr/nfpr is larger than possible
+WRITE_NXPR(nxpr);
+WRITE_NFPR(nfpr);
+uint32_t maxvl = 8 * (256 / (nxpr-1 + nfpr));
+WRITE_MAXVL(maxvl);
+WRITE_VL(0);
-require_vector;
-setvl(RS1);
-RD = VL;
+uint32_t vl = std::min(MAXVL, (uint32_t)XS1);
+WRITE_VL(vl);
+WRITE_XRD(vl);
+++ /dev/null
-require_vector;
-VEC_STORE(RD, store_uint16, 2);
+VEC_SEG_STORE(XPR, store_uint8, 1);
+VEC_SEG_STORE(XPR, store_uint64, 8);
+VEC_SEG_STORE(XPR, store_uint16, 2);
+VEC_SEG_ST_STORE(XPR, store_uint8, XS2, 1);
+VEC_SEG_ST_STORE(XPR, store_uint64, XS2, 8);
+VEC_SEG_ST_STORE(XPR, store_uint16, XS2, 2);
+VEC_SEG_ST_STORE(XPR, store_uint32, XS2, 4);
+VEC_SEG_STORE(XPR, store_uint32, 4);
+++ /dev/null
-require_vector;
-VEC_STORE(RD, store_uint8, RS2);
+++ /dev/null
-require_vector;
-require_xpr64;
-VEC_STORE(RD, store_uint64, RS2);
+++ /dev/null
-require_vector;
-VEC_STORE(RD, store_uint16, RS2);
+++ /dev/null
-require_vector;
-VEC_STORE(RD, store_uint32, RS2);
+++ /dev/null
-require_vector;
-VEC_STORE(RD, store_uint32, 4);
+++ /dev/null
-require_vector;
-nxpr_use = RS1 & 0x3f;
-nfpr_use = RS2 & 0x3f;
-vcfg();
-setvl(0);
+++ /dev/null
-require_vector;
-nxpr_use = RS1 & 0x3f;
-nfpr_use = RS2 & 0x3f;
-vcfg();
-setvl(0);
+++ /dev/null
-require_vector;
-nxpr_use = SIMM & 0x3f;
-nfpr_use = (SIMM >> 6) & 0x3f;
-vcfg();
-setvl(RS1);
-RD = VL;
--- /dev/null
+../../riscv/insns/add.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/addi.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/addiw.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/addw.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/amoadd_d.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/amoadd_w.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/amoand_d.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/amoand_w.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/amomax_d.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/amomax_w.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/amomaxu_d.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/amomaxu_w.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/amomin_d.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/amomin_w.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/amominu_d.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/amominu_w.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/amoor_d.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/amoor_w.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/amoswap_d.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/amoswap_w.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/amoxor_d.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/amoxor_w.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/and.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/andi.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/auipc.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/div.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/divu.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/divuw.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/divw.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/fadd_d.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/fadd_s.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/fcvt_d_l.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/fcvt_d_lu.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/fcvt_d_s.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/fcvt_d_w.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/fcvt_d_wu.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/fcvt_l_d.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/fcvt_l_s.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/fcvt_lu_d.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/fcvt_lu_s.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/fcvt_s_d.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/fcvt_s_l.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/fcvt_s_lu.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/fcvt_s_w.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/fcvt_s_wu.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/fcvt_w_d.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/fcvt_w_s.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/fcvt_wu_d.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/fcvt_wu_s.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/fdiv_d.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/fdiv_s.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/fence.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/feq_d.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/feq_s.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/fld.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/fle_d.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/fle_s.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/flt_d.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/flt_s.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/flw.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/fmadd_d.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/fmadd_s.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/fmax_d.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/fmax_s.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/fmin_d.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/fmin_s.h
\ No newline at end of file
--- /dev/null
+if (RS1 & 0x1) WRITE_FRD(FRS2);
--- /dev/null
+if (~RS1 & 0x1) WRITE_FRD(FRS2);
--- /dev/null
+../../riscv/insns/fmsub_d.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/fmsub_s.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/fmul_d.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/fmul_s.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/fmv_d_x.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/fmv_s_x.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/fmv_x_d.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/fmv_x_s.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/fnmadd_d.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/fnmadd_s.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/fnmsub_d.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/fnmsub_s.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/frsr.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/fsd.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/fsgnj_d.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/fsgnj_s.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/fsgnjn_d.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/fsgnjn_s.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/fsgnjx_d.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/fsgnjx_s.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/fsqrt_d.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/fsqrt_s.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/fssr.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/fsub_d.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/fsub_s.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/fsw.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/lb.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/lbu.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/ld.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/lh.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/lhu.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/lui.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/lw.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/lwu.h
\ No newline at end of file
--- /dev/null
+if (RS1 & 0x1) WRITE_RD(RS2);
--- /dev/null
+if (~RS1 & 0x1) WRITE_RD(RS2);
--- /dev/null
+../../riscv/insns/mul.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/mulh.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/mulhsu.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/mulhu.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/mulw.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/or.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/ori.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/rem.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/remu.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/remuw.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/remw.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/sb.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/sd.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/sh.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/sll.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/slli.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/slliw.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/sllw.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/slt.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/slti.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/sltiu.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/sltu.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/sra.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/srai.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/sraiw.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/sraw.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/srl.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/srli.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/srliw.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/srlw.h
\ No newline at end of file
--- /dev/null
+h->get_ut_state(UTIDX)->run = false;
--- /dev/null
+../../riscv/insns/sub.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/subw.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/sw.h
\ No newline at end of file
--- /dev/null
+WRITE_RD(UTIDX);
--- /dev/null
+../../riscv/insns/xor.h
\ No newline at end of file
--- /dev/null
+../../riscv/insns/xori.h
\ No newline at end of file
--- /dev/null
+DECLARE_INSN(vf, 0x10202b, 0x1f0707f)
+DECLARE_INSN(vflsegd, 0x1600205b, 0x1ff0707f)
+DECLARE_INSN(vflsegstd, 0x1600305b, 0x1e00707f)
+DECLARE_INSN(vflsegstw, 0x1400305b, 0x1e00707f)
+DECLARE_INSN(vflsegw, 0x1400205b, 0x1ff0707f)
+DECLARE_INSN(vfssegd, 0x1600207b, 0x1ff0707f)
+DECLARE_INSN(vfssegstd, 0x1600307b, 0x1e00707f)
+DECLARE_INSN(vfssegstw, 0x1400307b, 0x1e00707f)
+DECLARE_INSN(vfssegw, 0x1400207b, 0x1ff0707f)
+DECLARE_INSN(vgetcfg, 0x400b, 0xfffff07f)
+DECLARE_INSN(vgetvl, 0x200400b, 0xfffff07f)
+DECLARE_INSN(vlsegb, 0x205b, 0x1ff0707f)
+DECLARE_INSN(vlsegbu, 0x800205b, 0x1ff0707f)
+DECLARE_INSN(vlsegd, 0x600205b, 0x1ff0707f)
+DECLARE_INSN(vlsegh, 0x200205b, 0x1ff0707f)
+DECLARE_INSN(vlseghu, 0xa00205b, 0x1ff0707f)
+DECLARE_INSN(vlsegstb, 0x305b, 0x1e00707f)
+DECLARE_INSN(vlsegstbu, 0x800305b, 0x1e00707f)
+DECLARE_INSN(vlsegstd, 0x600305b, 0x1e00707f)
+DECLARE_INSN(vlsegsth, 0x200305b, 0x1e00707f)
+DECLARE_INSN(vlsegsthu, 0xa00305b, 0x1e00707f)
+DECLARE_INSN(vlsegstw, 0x400305b, 0x1e00707f)
+DECLARE_INSN(vlsegstwu, 0xc00305b, 0x1e00707f)
+DECLARE_INSN(vlsegw, 0x400205b, 0x1ff0707f)
+DECLARE_INSN(vlsegwu, 0xc00205b, 0x1ff0707f)
+DECLARE_INSN(vmsv, 0x200202b, 0xfff0707f)
+DECLARE_INSN(vmvv, 0x200002b, 0xfff0707f)
+DECLARE_INSN(vsetcfg, 0x200b, 0x7fff)
+DECLARE_INSN(vsetvl, 0x600b, 0xfff0707f)
+DECLARE_INSN(vssegb, 0x207b, 0x1ff0707f)
+DECLARE_INSN(vssegd, 0x600207b, 0x1ff0707f)
+DECLARE_INSN(vssegh, 0x200207b, 0x1ff0707f)
+DECLARE_INSN(vssegstb, 0x307b, 0x1e00707f)
+DECLARE_INSN(vssegstd, 0x600307b, 0x1e00707f)
+DECLARE_INSN(vssegsth, 0x200307b, 0x1e00707f)
+DECLARE_INSN(vssegstw, 0x400307b, 0x1e00707f)
+DECLARE_INSN(vssegw, 0x400207b, 0x1ff0707f)
+DECLARE_INSN(vxcptkill, 0x400302b, 0xffffffff)
+DECLARE_INSN(vxcptrestore, 0x200302b, 0xfff07fff)
+DECLARE_INSN(vxcptsave, 0x302b, 0xfff07fff)
--- /dev/null
+DECLARE_INSN(ut_movn, 0x2007077, 0xfe00707f)
+DECLARE_INSN(ut_movz, 0x7077, 0xfe00707f)
+DECLARE_INSN(ut_fmovn, 0x6007077, 0xfe00707f)
+DECLARE_INSN(ut_fmovz, 0x4007077, 0xfe00707f)
+DECLARE_INSN(ut_stop, 0x5077, 0xffffffff)
+DECLARE_INSN(ut_utidx, 0x6077, 0xfffff07f)
+DECLARE_INSN(ut_fmv_s_x, 0xf0000053, 0xfff0707f)
+DECLARE_INSN(ut_amoxor_w, 0x2000202f, 0xf800707f)
+DECLARE_INSN(ut_remuw, 0x200703b, 0xfe00707f)
+DECLARE_INSN(ut_fmin_d, 0xc2000053, 0xfe00707f)
+DECLARE_INSN(ut_amomax_d, 0xa000302f, 0xf800707f)
+DECLARE_INSN(ut_fmin_s, 0xc0000053, 0xfe00707f)
+DECLARE_INSN(ut_slliw, 0x4000101b, 0xfe00707f)
+DECLARE_INSN(ut_lb, 0x3, 0x707f)
+DECLARE_INSN(ut_fcvt_s_wu, 0x78000053, 0xfff0007f)
+DECLARE_INSN(ut_fcvt_d_l, 0x62000053, 0xfff0007f)
+DECLARE_INSN(ut_lh, 0x1003, 0x707f)
+DECLARE_INSN(ut_frsr, 0xe8000053, 0xfffff07f)
+DECLARE_INSN(ut_fcvt_d_w, 0x72000053, 0xfff0007f)
+DECLARE_INSN(ut_lw, 0x2003, 0x707f)
+DECLARE_INSN(ut_add, 0x33, 0xfe00707f)
+DECLARE_INSN(ut_fcvt_d_s, 0x82000053, 0xfff0007f)
+DECLARE_INSN(ut_fmax_d, 0xca000053, 0xfe00707f)
+DECLARE_INSN(ut_fcvt_s_d, 0x88000053, 0xfff0007f)
+DECLARE_INSN(ut_fadd_d, 0x2000053, 0xfe00007f)
+DECLARE_INSN(ut_sltiu, 0x3013, 0x707f)
+DECLARE_INSN(ut_fcvt_s_w, 0x70000053, 0xfff0007f)
+DECLARE_INSN(ut_mul, 0x2000033, 0xfe00707f)
+DECLARE_INSN(ut_amominu_d, 0xc000302f, 0xf800707f)
+DECLARE_INSN(ut_srli, 0x5013, 0xfc00707f)
+DECLARE_INSN(ut_amominu_w, 0xc000202f, 0xf800707f)
+DECLARE_INSN(ut_divuw, 0x200503b, 0xfe00707f)
+DECLARE_INSN(ut_mulw, 0x200003b, 0xfe00707f)
+DECLARE_INSN(ut_srlw, 0x503b, 0xfe00707f)
+DECLARE_INSN(ut_div, 0x2004033, 0xfe00707f)
+DECLARE_INSN(ut_fdiv_d, 0x1a000053, 0xfe00007f)
+DECLARE_INSN(ut_fence, 0xf, 0x707f)
+DECLARE_INSN(ut_fnmsub_s, 0x4b, 0x600007f)
+DECLARE_INSN(ut_fcvt_l_s, 0x40000053, 0xfff0007f)
+DECLARE_INSN(ut_fle_s, 0xb8000053, 0xfe00707f)
+DECLARE_INSN(ut_fdiv_s, 0x18000053, 0xfe00007f)
+DECLARE_INSN(ut_fle_d, 0xba000053, 0xfe00707f)
+DECLARE_INSN(ut_fnmsub_d, 0x200004b, 0x600007f)
+DECLARE_INSN(ut_addw, 0x3b, 0xfe00707f)
+DECLARE_INSN(ut_sll, 0x1033, 0xfe00707f)
+DECLARE_INSN(ut_xor, 0x4033, 0xfe00707f)
+DECLARE_INSN(ut_sub, 0x40000033, 0xfe00707f)
+DECLARE_INSN(ut_rem, 0x2006033, 0xfe00707f)
+DECLARE_INSN(ut_srliw, 0x501b, 0xfe00707f)
+DECLARE_INSN(ut_lui, 0x37, 0x7f)
+DECLARE_INSN(ut_fcvt_s_lu, 0x68000053, 0xfff0007f)
+DECLARE_INSN(ut_addi, 0x13, 0x707f)
+DECLARE_INSN(ut_mulh, 0x2001033, 0xfe00707f)
+DECLARE_INSN(ut_fmul_s, 0x10000053, 0xfe00007f)
+DECLARE_INSN(ut_srai, 0x40005013, 0xfc00707f)
+DECLARE_INSN(ut_amoand_d, 0x6000302f, 0xf800707f)
+DECLARE_INSN(ut_flt_d, 0xb2000053, 0xfe00707f)
+DECLARE_INSN(ut_sraw, 0x4000503b, 0xfe00707f)
+DECLARE_INSN(ut_fmul_d, 0x12000053, 0xfe00007f)
+DECLARE_INSN(ut_ld, 0x3003, 0x707f)
+DECLARE_INSN(ut_ori, 0x6013, 0x707f)
+DECLARE_INSN(ut_flt_s, 0xb0000053, 0xfe00707f)
+DECLARE_INSN(ut_addiw, 0x1b, 0x707f)
+DECLARE_INSN(ut_amoand_w, 0x6000202f, 0xf800707f)
+DECLARE_INSN(ut_feq_s, 0xa8000053, 0xfe00707f)
+DECLARE_INSN(ut_fsgnjx_d, 0x3a000053, 0xfe00707f)
+DECLARE_INSN(ut_sra, 0x40005033, 0xfe00707f)
+DECLARE_INSN(ut_sraiw, 0x4000501b, 0xfe00707f)
+DECLARE_INSN(ut_srl, 0x5033, 0xfe00707f)
+DECLARE_INSN(ut_fsub_d, 0xa000053, 0xfe00007f)
+DECLARE_INSN(ut_fsgnjx_s, 0x38000053, 0xfe00707f)
+DECLARE_INSN(ut_feq_d, 0xaa000053, 0xfe00707f)
+DECLARE_INSN(ut_fcvt_d_wu, 0x7a000053, 0xfff0007f)
+DECLARE_INSN(ut_or, 0x6033, 0xfe00707f)
+DECLARE_INSN(ut_fcvt_wu_d, 0x5a000053, 0xfff0007f)
+DECLARE_INSN(ut_subw, 0x4000003b, 0xfe00707f)
+DECLARE_INSN(ut_fmax_s, 0xc8000053, 0xfe00707f)
+DECLARE_INSN(ut_amomaxu_d, 0xe000302f, 0xf800707f)
+DECLARE_INSN(ut_xori, 0x4013, 0x707f)
+DECLARE_INSN(ut_amoxor_d, 0x2000302f, 0xf800707f)
+DECLARE_INSN(ut_amomaxu_w, 0xe000202f, 0xf800707f)
+DECLARE_INSN(ut_fcvt_wu_s, 0x58000053, 0xfff0007f)
+DECLARE_INSN(ut_andi, 0x7013, 0x707f)
+DECLARE_INSN(ut_fmv_x_s, 0xe0000053, 0xfff0707f)
+DECLARE_INSN(ut_fsgnjn_d, 0x32000053, 0xfe00707f)
+DECLARE_INSN(ut_fnmadd_s, 0x4f, 0x600007f)
+DECLARE_INSN(ut_lwu, 0x6003, 0x707f)
+DECLARE_INSN(ut_fmv_x_d, 0xe2000053, 0xfff0707f)
+DECLARE_INSN(ut_fnmadd_d, 0x200004f, 0x600007f)
+DECLARE_INSN(ut_amoadd_d, 0x302f, 0xf800707f)
+DECLARE_INSN(ut_fcvt_w_s, 0x50000053, 0xfff0007f)
+DECLARE_INSN(ut_mulhsu, 0x2002033, 0xfe00707f)
+DECLARE_INSN(ut_amoadd_w, 0x202f, 0xf800707f)
+DECLARE_INSN(ut_fcvt_d_lu, 0x6a000053, 0xfff0007f)
+DECLARE_INSN(ut_fcvt_w_d, 0x52000053, 0xfff0007f)
+DECLARE_INSN(ut_slt, 0x2033, 0xfe00707f)
+DECLARE_INSN(ut_sllw, 0x103b, 0xfe00707f)
+DECLARE_INSN(ut_amoor_d, 0x4000302f, 0xf800707f)
+DECLARE_INSN(ut_slti, 0x2013, 0x707f)
+DECLARE_INSN(ut_remu, 0x2007033, 0xfe00707f)
+DECLARE_INSN(ut_flw, 0x2007, 0x707f)
+DECLARE_INSN(ut_remw, 0x200603b, 0xfe00707f)
+DECLARE_INSN(ut_sltu, 0x3033, 0xfe00707f)
+DECLARE_INSN(ut_slli, 0x40001013, 0xfc00707f)
+DECLARE_INSN(ut_amoor_w, 0x4000202f, 0xf800707f)
+DECLARE_INSN(ut_fld, 0x3007, 0x707f)
+DECLARE_INSN(ut_fsub_s, 0x8000053, 0xfe00007f)
+DECLARE_INSN(ut_and, 0x7033, 0xfe00707f)
+DECLARE_INSN(ut_fmv_d_x, 0xf2000053, 0xfff0707f)
+DECLARE_INSN(ut_lbu, 0x4003, 0x707f)
+DECLARE_INSN(ut_fsgnj_s, 0x28000053, 0xfe00707f)
+DECLARE_INSN(ut_amomax_w, 0xa000202f, 0xf800707f)
+DECLARE_INSN(ut_fsgnj_d, 0x2a000053, 0xfe00707f)
+DECLARE_INSN(ut_mulhu, 0x2003033, 0xfe00707f)
+DECLARE_INSN(ut_fcvt_l_d, 0x42000053, 0xfff0007f)
+DECLARE_INSN(ut_fssr, 0xf8000053, 0xfff0707f)
+DECLARE_INSN(ut_fcvt_lu_s, 0x48000053, 0xfff0007f)
+DECLARE_INSN(ut_fcvt_s_l, 0x60000053, 0xfff0007f)
+DECLARE_INSN(ut_auipc, 0x17, 0x7f)
+DECLARE_INSN(ut_fcvt_lu_d, 0x4a000053, 0xfff0007f)
+DECLARE_INSN(ut_fmadd_s, 0x43, 0x600007f)
+DECLARE_INSN(ut_fsqrt_s, 0x20000053, 0xfff0007f)
+DECLARE_INSN(ut_amomin_w, 0x8000202f, 0xf800707f)
+DECLARE_INSN(ut_fsgnjn_s, 0x30000053, 0xfe00707f)
+DECLARE_INSN(ut_amoswap_d, 0x800302f, 0xf800707f)
+DECLARE_INSN(ut_fsqrt_d, 0x22000053, 0xfff0007f)
+DECLARE_INSN(ut_fmadd_d, 0x2000043, 0x600007f)
+DECLARE_INSN(ut_divw, 0x200403b, 0xfe00707f)
+DECLARE_INSN(ut_amomin_d, 0x8000302f, 0xf800707f)
+DECLARE_INSN(ut_divu, 0x2005033, 0xfe00707f)
+DECLARE_INSN(ut_amoswap_w, 0x800202f, 0xf800707f)
+DECLARE_INSN(ut_fadd_s, 0x53, 0xfe00007f)
+DECLARE_INSN(ut_fsd, 0x3027, 0x707f)
+DECLARE_INSN(ut_sw, 0x2023, 0x707f)
+DECLARE_INSN(ut_fmsub_s, 0x47, 0x600007f)
+DECLARE_INSN(ut_lhu, 0x5003, 0x707f)
+DECLARE_INSN(ut_sh, 0x1023, 0x707f)
+DECLARE_INSN(ut_fsw, 0x2027, 0x707f)
+DECLARE_INSN(ut_sb, 0x23, 0x707f)
+DECLARE_INSN(ut_fmsub_d, 0x2000047, 0x600007f)
+DECLARE_INSN(ut_sd, 0x3023, 0x707f)
#include "extension.h"
#include "trap.h"
#include "dummy-rocc.h"
+#include "hwacha.h"
std::map<std::string, std::function<extension_t*()>>& extensions()
{
+++ /dev/null
-require_supervisor;
riscv_subproject_deps = \
softfloat_riscv \
softfloat \
+ hwacha \
riscv_install_prog_srcs = \
spike.cc \
#include "trap.h"
#include <cstdlib>
-union rocc_insn_union_t
-{
- rocc_insn_t r;
- insn_t i;
-};
-
#define customX(n) \
static reg_t c##n(processor_t* p, insn_t insn, reg_t pc) \
{ \
unsigned funct : 7;
};
+union rocc_insn_union_t
+{
+ rocc_insn_t r;
+ insn_t i;
+};
+
class rocc_t : public extension_t
{
public:
fprintf(stderr, " --ic=<S>:<W>:<B> Instantiate a cache model with S sets,\n");
fprintf(stderr, " --dc=<S>:<W>:<B> W ways, and B-byte blocks (with S and\n");
fprintf(stderr, " --l2=<S>:<W>:<B> B both powers of 2).\n");
+ fprintf(stderr, " --extension=<name> Specify RoCC Extension\n");
exit(1);
}
projects / riscv-isa-sim.git / commitdiff