8 static void dfii_setcontrol(const struct gramCtx
*ctx
, uint8_t val
) {
10 gram_write(ctx
, (void*)&(ctx
->core
->control
), val
);
12 ctx
->core
->control
= val
;
16 void dfii_setsw(const struct gramCtx
*ctx
, bool software_control
) {
17 if (software_control
) {
18 dfii_setcontrol(ctx
, DFII_CONTROL_CKE
|DFII_CONTROL_ODT
|DFII_CONTROL_RESET
|DFII_COMMAND_CS
);
20 dfii_setcontrol(ctx
, DFII_CONTROL_SEL
|DFII_CONTROL_RESET
);
24 void dfii_set_p0_address(const struct gramCtx
*ctx
, uint32_t val
) {
26 gram_write(ctx
, (void*)&(ctx
->core
->phases
[0].address
), val
);
28 ctx
->core
->phases
[0].address
= val
;
32 void dfii_set_p0_baddress(const struct gramCtx
*ctx
, uint32_t val
) {
34 gram_write(ctx
, (void*)&(ctx
->core
->phases
[0].baddress
), val
);
36 ctx
->core
->phases
[0].baddress
= val
;
40 void dfii_p0_command(const struct gramCtx
*ctx
, uint32_t cmd
) {
42 gram_write(ctx
, (void*)&(ctx
->core
->phases
[0].command
), cmd
);
43 gram_write(ctx
, (void*)&(ctx
->core
->phases
[0].command_issue
), 1);
45 ctx
->core
->phases
[0].command
= cmd
;
46 ctx
->core
->phases
[0].command_issue
= 1;
50 /* Set MRx register */
51 static void dfii_set_mr(const struct gramCtx
*ctx
, uint8_t mr
, uint16_t val
) {
52 dfii_set_p0_address(ctx
, val
);
53 dfii_set_p0_baddress(ctx
, mr
);
54 dfii_p0_command(ctx
, DFII_COMMAND_RAS
|DFII_COMMAND_CAS
|DFII_COMMAND_WE
|DFII_COMMAND_CS
);
57 #define MR0_DLL_RESET (1 << 8)
58 void dfii_initseq(const struct gramCtx
*ctx
, const struct gramProfile
*profile
) {
60 dfii_set_p0_address(ctx
, 0x0);
61 dfii_set_p0_baddress(ctx
, 0);
62 dfii_setcontrol(ctx
, 0);
66 dfii_set_p0_address(ctx
, 0x0);
67 dfii_set_p0_baddress(ctx
, 0);
68 dfii_setcontrol(ctx
, DFII_CONTROL_ODT
|DFII_CONTROL_RESET
);
72 dfii_set_p0_address(ctx
, 0x0);
73 dfii_set_p0_baddress(ctx
, 0);
74 dfii_setcontrol(ctx
, DFII_CONTROL_CKE
|DFII_CONTROL_ODT
|DFII_CONTROL_RESET
);
77 /* Load Mode Register 2, CWL=5 */
78 dfii_set_mr(ctx
, 2, profile
->mode_registers
[2]);
80 /* Load Mode Register 3 */
81 dfii_set_mr(ctx
, 3, profile
->mode_registers
[3]);
83 /* Load Mode Register 1 */
84 dfii_set_mr(ctx
, 1, profile
->mode_registers
[1]);
86 /* Load Mode Register 0, CL=6, BL=8 */
87 dfii_set_mr(ctx
, 0, profile
->mode_registers
[0]);
88 if (profile
->mode_registers
[0] & MR0_DLL_RESET
) {
90 dfii_set_mr(ctx
, 0, profile
->mode_registers
[0] & ~MR0_DLL_RESET
);
95 dfii_set_p0_address(ctx
, 0x400);
96 dfii_set_p0_baddress(ctx
, 0);
97 dfii_p0_command(ctx
, DFII_COMMAND_WE
|DFII_COMMAND_CS
);