loadstore1.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7 use work.common.all;
   8 use work.insn_helpers.all;
   9 use work.helpers.all;
  10
  11 -- 2 cycle LSU
  12 -- We calculate the address in the first cycle
  13
  14 entity loadstore1 is
  15     generic (
  16         HAS_FPU : boolean := true;
  17         -- Non-zero to enable log data collection
  18         LOG_LENGTH : natural := 0
  19         );
  20     port (
  21         clk   : in std_ulogic;
  22         rst   : in std_ulogic;
  23
  24         l_in  : in Execute1ToLoadstore1Type;
  25         e_out : out Loadstore1ToExecute1Type;
  26         l_out : out Loadstore1ToWritebackType;
  27
  28         d_out : out Loadstore1ToDcacheType;
  29         d_in  : in DcacheToLoadstore1Type;
  30
  31         m_out : out Loadstore1ToMmuType;
  32         m_in  : in MmuToLoadstore1Type;
  33
  34         dc_stall  : in std_ulogic;
  35
  36         log_out : out std_ulogic_vector(9 downto 0)
  37         );
  38 end loadstore1;
  39
  40 -- Note, we don't currently use the stall output from the dcache because
  41 -- we know it can take two requests without stalling when idle, we are
  42 -- its only user, and we know it never stalls when idle.
  43
  44 architecture behave of loadstore1 is
  45
  46     -- State machine for unaligned loads/stores
  47     type state_t is (IDLE,              -- ready for instruction
  48                      SECOND_REQ,        -- send 2nd request of unaligned xfer
  49                      ACK_WAIT,          -- waiting for ack from dcache
  50                      MMU_LOOKUP,        -- waiting for MMU to look up translation
  51                      TLBIE_WAIT,        -- waiting for MMU to finish doing a tlbie
  52                      FINISH_LFS,        -- write back converted SP data for lfs*
  53                      COMPLETE           -- extra cycle to complete an operation
  54                      );
  55
  56     type byte_index_t is array(0 to 7) of unsigned(2 downto 0);
  57     subtype byte_trim_t is std_ulogic_vector(1 downto 0);
  58     type trim_ctl_t is array(0 to 7) of byte_trim_t;
  59
  60     type reg_stage_t is record
  61         -- latch most of the input request
  62         load         : std_ulogic;
  63         tlbie        : std_ulogic;
  64         dcbz         : std_ulogic;
  65         addr         : std_ulogic_vector(63 downto 0);
  66         store_data   : std_ulogic_vector(63 downto 0);
  67         load_data    : std_ulogic_vector(63 downto 0);
  68         write_reg    : gspr_index_t;
  69         length       : std_ulogic_vector(3 downto 0);
  70         byte_reverse : std_ulogic;
  71         byte_offset  : unsigned(2 downto 0);
  72         brev_mask    : unsigned(2 downto 0);
  73         sign_extend  : std_ulogic;
  74         update       : std_ulogic;
  75         update_reg   : gpr_index_t;
  76         xerc         : xer_common_t;
  77         reserve      : std_ulogic;
  78         atomic       : std_ulogic;
  79         atomic_last  : std_ulogic;
  80         rc           : std_ulogic;
  81         nc           : std_ulogic;              -- non-cacheable access
  82         virt_mode    : std_ulogic;
  83         priv_mode    : std_ulogic;
  84         state        : state_t;
  85         dwords_done  : std_ulogic;
  86         last_dword   : std_ulogic;
  87         first_bytes  : std_ulogic_vector(7 downto 0);
  88         second_bytes : std_ulogic_vector(7 downto 0);
  89         dar          : std_ulogic_vector(63 downto 0);
  90         dsisr        : std_ulogic_vector(31 downto 0);
  91         instr_fault  : std_ulogic;
  92         align_intr   : std_ulogic;
  93         sprval       : std_ulogic_vector(63 downto 0);
  94         busy         : std_ulogic;
  95         wait_dcache  : std_ulogic;
  96         wait_mmu     : std_ulogic;
  97         do_update    : std_ulogic;
  98         extra_cycle  : std_ulogic;
  99         mode_32bit   : std_ulogic;
 100         byte_index   : byte_index_t;
 101         use_second   : std_ulogic_vector(7 downto 0);
 102         trim_ctl     : trim_ctl_t;
 103         load_sp      : std_ulogic;
 104         ld_sp_data   : std_ulogic_vector(31 downto 0);
 105         ld_sp_nz     : std_ulogic;
 106         ld_sp_lz     : std_ulogic_vector(5 downto 0);
 107         wr_sel       : std_ulogic_vector(1 downto 0);
 108     end record;
 109
 110     signal r, rin : reg_stage_t;
 111     signal lsu_sum : std_ulogic_vector(63 downto 0);
 112
 113     signal store_sp_data : std_ulogic_vector(31 downto 0);
 114     signal load_dp_data  : std_ulogic_vector(63 downto 0);
 115
 116     -- Generate byte enables from sizes
 117     function length_to_sel(length : in std_logic_vector(3 downto 0)) return std_ulogic_vector is
 118     begin
 119         case length is
 120             when "0001" =>
 121                 return "00000001";
 122             when "0010" =>
 123                 return "00000011";
 124             when "0100" =>
 125                 return "00001111";
 126             when "1000" =>
 127                 return "11111111";
 128             when others =>
 129                 return "00000000";
 130         end case;
 131     end function length_to_sel;
 132
 133     -- Calculate byte enables
 134     -- This returns 16 bits, giving the select signals for two transfers,
 135     -- to account for unaligned loads or stores
 136     function xfer_data_sel(size : in std_logic_vector(3 downto 0);
 137                            address : in std_logic_vector(2 downto 0))
 138         return std_ulogic_vector is
 139         variable longsel : std_ulogic_vector(15 downto 0);
 140     begin
 141         longsel := "00000000" & length_to_sel(size);
 142         return std_ulogic_vector(shift_left(unsigned(longsel),
 143                                             to_integer(unsigned(address))));
 144     end function xfer_data_sel;
 145
 146     -- 23-bit right shifter for DP -> SP float conversions
 147     function shifter_23r(frac: std_ulogic_vector(22 downto 0); shift: unsigned(4 downto 0))
 148         return std_ulogic_vector is
 149         variable fs1   : std_ulogic_vector(22 downto 0);
 150         variable fs2   : std_ulogic_vector(22 downto 0);
 151     begin
 152         case shift(1 downto 0) is
 153             when "00" =>
 154                 fs1 := frac;
 155             when "01" =>
 156                 fs1 := '0' & frac(22 downto 1);
 157             when "10" =>
 158                 fs1 := "00" & frac(22 downto 2);
 159             when others =>
 160                 fs1 := "000" & frac(22 downto 3);
 161         end case;
 162         case shift(4 downto 2) is
 163             when "000" =>
 164                 fs2 := fs1;
 165             when "001" =>
 166                 fs2 := x"0" & fs1(22 downto 4);
 167             when "010" =>
 168                 fs2 := x"00" & fs1(22 downto 8);
 169             when "011" =>
 170                 fs2 := x"000" & fs1(22 downto 12);
 171             when "100" =>
 172                 fs2 := x"0000" & fs1(22 downto 16);
 173             when others =>
 174                 fs2 := x"00000" & fs1(22 downto 20);
 175         end case;
 176         return fs2;
 177     end;
 178
 179     -- 23-bit left shifter for SP -> DP float conversions
 180     function shifter_23l(frac: std_ulogic_vector(22 downto 0); shift: unsigned(4 downto 0))
 181         return std_ulogic_vector is
 182         variable fs1   : std_ulogic_vector(22 downto 0);
 183         variable fs2   : std_ulogic_vector(22 downto 0);
 184     begin
 185         case shift(1 downto 0) is
 186             when "00" =>
 187                 fs1 := frac;
 188             when "01" =>
 189                 fs1 := frac(21 downto 0) & '0';
 190             when "10" =>
 191                 fs1 := frac(20 downto 0) & "00";
 192             when others =>
 193                 fs1 := frac(19 downto 0) & "000";
 194         end case;
 195         case shift(4 downto 2) is
 196             when "000" =>
 197                 fs2 := fs1;
 198             when "001" =>
 199                 fs2 := fs1(18 downto 0) & x"0" ;
 200             when "010" =>
 201                 fs2 := fs1(14 downto 0) & x"00";
 202             when "011" =>
 203                 fs2 := fs1(10 downto 0) & x"000";
 204             when "100" =>
 205                 fs2 := fs1(6 downto 0) & x"0000";
 206             when others =>
 207                 fs2 := fs1(2 downto 0) & x"00000";
 208         end case;
 209         return fs2;
 210     end;
 211
 212 begin
 213     -- Calculate the address in the first cycle
 214     lsu_sum <= std_ulogic_vector(unsigned(l_in.addr1) + unsigned(l_in.addr2)) when l_in.valid = '1' else (others => '0');
 215
 216     loadstore1_0: process(clk)
 217     begin
 218         if rising_edge(clk) then
 219             if rst = '1' then
 220                 r.state <= IDLE;
 221                 r.busy <= '0';
 222                 r.do_update <= '0';
 223             else
 224                 r <= rin;
 225             end if;
 226         end if;
 227     end process;
 228
 229     ls_fp_conv: if HAS_FPU generate
 230         -- Convert DP data to SP for stfs
 231         dp_to_sp: process(all)
 232             variable exp   : unsigned(10 downto 0);
 233             variable frac  : std_ulogic_vector(22 downto 0);
 234             variable shift : unsigned(4 downto 0);
 235         begin
 236             store_sp_data(31) <= l_in.data(63);
 237             store_sp_data(30 downto 0) <= (others => '0');
 238             exp := unsigned(l_in.data(62 downto 52));
 239             if exp > 896 then
 240                 store_sp_data(30) <= l_in.data(62);
 241                 store_sp_data(29 downto 0) <= l_in.data(58 downto 29);
 242             elsif exp >= 874 then
 243                 -- denormalization required
 244                 frac := '1' & l_in.data(51 downto 30);
 245                 shift := 0 - exp(4 downto 0);
 246                 store_sp_data(22 downto 0) <= shifter_23r(frac, shift);
 247             end if;
 248         end process;
 249
 250         -- Convert SP data to DP for lfs
 251         sp_to_dp: process(all)
 252             variable exp     : unsigned(7 downto 0);
 253             variable exp_dp  : unsigned(10 downto 0);
 254             variable exp_nz  : std_ulogic;
 255             variable exp_ao  : std_ulogic;
 256             variable frac    : std_ulogic_vector(22 downto 0);
 257             variable frac_shift : unsigned(4 downto 0);
 258         begin
 259             frac := r.ld_sp_data(22 downto 0);
 260             exp := unsigned(r.ld_sp_data(30 downto 23));
 261             exp_nz := or (r.ld_sp_data(30 downto 23));
 262             exp_ao := and (r.ld_sp_data(30 downto 23));
 263             frac_shift := (others => '0');
 264             if exp_ao = '1' then
 265                 exp_dp := to_unsigned(2047, 11);    -- infinity or NaN
 266             elsif exp_nz = '1' then
 267                 exp_dp := 896 + resize(exp, 11);    -- finite normalized value
 268             elsif r.ld_sp_nz = '0' then
 269                 exp_dp := to_unsigned(0, 11);       -- zero
 270             else
 271                 -- denormalized SP operand, need to normalize
 272                 exp_dp := 896 - resize(unsigned(r.ld_sp_lz), 11);
 273                 frac_shift := unsigned(r.ld_sp_lz(4 downto 0)) + 1;
 274             end if;
 275             load_dp_data(63) <= r.ld_sp_data(31);
 276             load_dp_data(62 downto 52) <= std_ulogic_vector(exp_dp);
 277             load_dp_data(51 downto 29) <= shifter_23l(frac, frac_shift);
 278             load_dp_data(28 downto 0) <= (others => '0');
 279         end process;
 280     end generate;
 281
 282     loadstore1_1: process(all)
 283         variable v : reg_stage_t;
 284         variable brev_lenm1 : unsigned(2 downto 0);
 285         variable byte_offset : unsigned(2 downto 0);
 286         variable j : integer;
 287         variable k : unsigned(2 downto 0);
 288         variable kk : unsigned(3 downto 0);
 289         variable long_sel : std_ulogic_vector(15 downto 0);
 290         variable byte_sel : std_ulogic_vector(7 downto 0);
 291         variable req : std_ulogic;
 292         variable busy : std_ulogic;
 293         variable addr : std_ulogic_vector(63 downto 0);
 294         variable maddr : std_ulogic_vector(63 downto 0);
 295         variable wdata : std_ulogic_vector(63 downto 0);
 296         variable write_enable : std_ulogic;
 297         variable do_update : std_ulogic;
 298         variable done : std_ulogic;
 299         variable data_permuted : std_ulogic_vector(63 downto 0);
 300         variable data_trimmed : std_ulogic_vector(63 downto 0);
 301         variable store_data : std_ulogic_vector(63 downto 0);
 302         variable byte_rev : std_ulogic;
 303         variable length : std_ulogic_vector(3 downto 0);
 304         variable negative : std_ulogic;
 305         variable sprn : std_ulogic_vector(9 downto 0);
 306         variable exception : std_ulogic;
 307         variable next_addr : std_ulogic_vector(63 downto 0);
 308         variable mmureq : std_ulogic;
 309         variable dsisr : std_ulogic_vector(31 downto 0);
 310         variable mmu_mtspr : std_ulogic;
 311         variable itlb_fault : std_ulogic;
 312         variable misaligned : std_ulogic;
 313     begin
 314         v := r;
 315         req := '0';
 316         mmu_mtspr := '0';
 317         itlb_fault := '0';
 318         sprn := std_ulogic_vector(to_unsigned(decode_spr_num(l_in.insn), 10));
 319         dsisr := (others => '0');
 320         mmureq := '0';
 321         v.wr_sel := "11";
 322
 323         write_enable := '0';
 324
 325         do_update := r.do_update;
 326         v.do_update := '0';
 327
 328         -- load data formatting
 329         -- shift and byte-reverse data bytes
 330         for i in 0 to 7 loop
 331             j := to_integer(r.byte_index(i)) * 8;
 332             data_permuted(i * 8 + 7 downto i * 8) := d_in.data(j + 7 downto j);
 333         end loop;
 334
 335         -- Work out the sign bit for sign extension.
 336         -- For unaligned loads crossing two dwords, the sign bit is in the
 337         -- first dword for big-endian (byte_reverse = 1), or the second dword
 338         -- for little-endian.
 339         if r.dwords_done = '1' and r.byte_reverse = '1' then
 340             negative := (r.length(3) and r.load_data(63)) or
 341                         (r.length(2) and r.load_data(31)) or
 342                         (r.length(1) and r.load_data(15)) or
 343                         (r.length(0) and r.load_data(7));
 344         else
 345             negative := (r.length(3) and data_permuted(63)) or
 346                         (r.length(2) and data_permuted(31)) or
 347                         (r.length(1) and data_permuted(15)) or
 348                         (r.length(0) and data_permuted(7));
 349         end if;
 350
 351         -- trim and sign-extend
 352         for i in 0 to 7 loop
 353             case r.trim_ctl(i) is
 354                 when "11" =>
 355                     data_trimmed(i * 8 + 7 downto i * 8) := r.load_data(i * 8 + 7 downto i * 8);
 356                 when "10" =>
 357                     data_trimmed(i * 8 + 7 downto i * 8) := data_permuted(i * 8 + 7 downto i * 8);
 358                 when "01" =>
 359                     data_trimmed(i * 8 + 7 downto i * 8) := (others => negative);
 360                 when others =>
 361                     data_trimmed(i * 8 + 7 downto i * 8) := x"00";
 362             end case;
 363         end loop;
 364
 365         if HAS_FPU then
 366             -- Single-precision FP conversion for loads
 367             v.ld_sp_data := data_trimmed(31 downto 0);
 368             v.ld_sp_nz := or (data_trimmed(22 downto 0));
 369             v.ld_sp_lz := count_left_zeroes(data_trimmed(22 downto 0));
 370         end if;
 371
 372         -- Byte reversing and rotating for stores.
 373         -- Done in the second cycle (the cycle after l_in.valid = 1).
 374         for i in 0 to 7 loop
 375             k := (to_unsigned(i, 3) - r.byte_offset) xor r.brev_mask;
 376             j := to_integer(k) * 8;
 377             store_data(i * 8 + 7 downto i * 8) := r.store_data(j + 7 downto j);
 378         end loop;
 379
 380         -- compute (addr + 8) & ~7 for the second doubleword when unaligned
 381         next_addr := std_ulogic_vector(unsigned(r.addr(63 downto 3)) + 1) & "000";
 382
 383         -- Busy calculation.
 384         -- We need to minimize the delay from clock to busy valid because it
 385         -- gates the start of execution of the next instruction.
 386         busy := r.busy and not ((r.wait_dcache and d_in.valid) or (r.wait_mmu and m_in.done));
 387         v.busy := busy;
 388
 389         done := '0';
 390         if r.state /= IDLE and busy = '0' then
 391             done := '1';
 392         end if;
 393         exception := '0';
 394
 395         if r.dwords_done = '1' or r.state = SECOND_REQ then
 396             addr := next_addr;
 397             byte_sel := r.second_bytes;
 398         else
 399             addr := r.addr;
 400             byte_sel := r.first_bytes;
 401         end if;
 402         if r.mode_32bit = '1' then
 403             addr(63 downto 32) := (others => '0');
 404         end if;
 405         maddr := addr;
 406
 407         case r.state is
 408         when IDLE =>
 409
 410         when SECOND_REQ =>
 411             req := '1';
 412             v.state := ACK_WAIT;
 413             v.last_dword := '0';
 414
 415         when ACK_WAIT =>
 416             -- r.wr_sel gets set one cycle after we come into ACK_WAIT state,
 417             -- which is OK because the dcache always takes at least two cycles.
 418             if r.update = '1' and (r.load = '0' or (HAS_FPU and r.load_sp = '1')) then
 419                 v.wr_sel := "01";
 420             end if;
 421             if d_in.error = '1' then
 422                 -- dcache will discard the second request if it
 423                 -- gets an error on the 1st of two requests
 424                 if d_in.cache_paradox = '1' then
 425                     -- signal an interrupt straight away
 426                     exception := '1';
 427                     dsisr(63 - 38) := not r.load;
 428                     -- XXX there is no architected bit for this
 429                     dsisr(63 - 35) := d_in.cache_paradox;
 430                 else
 431                     -- Look up the translation for TLB miss
 432                     -- and also for permission error and RC error
 433                     -- in case the PTE has been updated.
 434                     mmureq := '1';
 435                     v.state := MMU_LOOKUP;
 436                 end if;
 437             end if;
 438             if d_in.valid = '1' then
 439                 if r.last_dword = '0' then
 440                     v.dwords_done := '1';
 441                     v.last_dword := '1';
 442                     if r.load = '1' then
 443                         v.load_data := data_permuted;
 444                     end if;
 445                 else
 446                     write_enable := r.load and not r.load_sp;
 447                     if HAS_FPU and r.load_sp = '1' then
 448                         -- SP to DP conversion takes a cycle
 449                         -- Write back rA update in this cycle if needed
 450                         do_update := r.update;
 451                         v.wr_sel := "10";
 452                         v.state := FINISH_LFS;
 453                     elsif r.extra_cycle = '1' then
 454                         -- loads with rA update need an extra cycle
 455                         v.wr_sel := "01";
 456                         v.state := COMPLETE;
 457                         v.do_update := r.update;
 458                     else
 459                         -- stores write back rA update in this cycle
 460                         do_update := r.update;
 461                     end if;
 462                     v.busy := '0';
 463                 end if;
 464             end if;
 465             -- r.wait_dcache gets set one cycle after we come into ACK_WAIT state,
 466             -- which is OK because the dcache always takes at least two cycles.
 467             v.wait_dcache := r.last_dword and not r.extra_cycle;
 468
 469         when MMU_LOOKUP =>
 470             if m_in.done = '1' then
 471                 if r.instr_fault = '0' then
 472                     -- retry the request now that the MMU has installed a TLB entry
 473                     req := '1';
 474                     if r.last_dword = '0' then
 475                         v.state := SECOND_REQ;
 476                     else
 477                         v.state := ACK_WAIT;
 478                     end if;
 479                 end if;
 480             end if;
 481             if m_in.err = '1' then
 482                 exception := '1';
 483                 dsisr(63 - 33) := m_in.invalid;
 484                 dsisr(63 - 36) := m_in.perm_error;
 485                 dsisr(63 - 38) := not r.load;
 486                 dsisr(63 - 44) := m_in.badtree;
 487                 dsisr(63 - 45) := m_in.rc_error;
 488             end if;
 489
 490         when TLBIE_WAIT =>
 491
 492         when FINISH_LFS =>
 493
 494         when COMPLETE =>
 495             exception := r.align_intr;
 496
 497         end case;
 498
 499         if done = '1' or exception = '1' then
 500             v.state := IDLE;
 501             v.busy := '0';
 502         end if;
 503
 504         -- Note that l_in.valid is gated with busy inside execute1
 505         if l_in.valid = '1' then
 506             v.mode_32bit := l_in.mode_32bit;
 507             v.load := '0';
 508             v.dcbz := '0';
 509             v.tlbie := '0';
 510             v.instr_fault := '0';
 511             v.align_intr := '0';
 512             v.dwords_done := '0';
 513             v.last_dword := '1';
 514             v.write_reg := l_in.write_reg;
 515             v.length := l_in.length;
 516             v.byte_reverse := l_in.byte_reverse;
 517             v.sign_extend := l_in.sign_extend;
 518             v.update := l_in.update;
 519             v.update_reg := l_in.update_reg;
 520             v.xerc := l_in.xerc;
 521             v.reserve := l_in.reserve;
 522             v.rc := l_in.rc;
 523             v.nc := l_in.ci;
 524             v.virt_mode := l_in.virt_mode;
 525             v.priv_mode := l_in.priv_mode;
 526             v.load_sp := '0';
 527             v.wait_dcache := '0';
 528             v.wait_mmu := '0';
 529             v.do_update := '0';
 530             v.extra_cycle := '0';
 531
 532             if HAS_FPU and l_in.is_32bit = '1' then
 533                 v.store_data := x"00000000" & store_sp_data;
 534             else
 535                 v.store_data := l_in.data;
 536             end if;
 537
 538             addr := lsu_sum;
 539             if l_in.second = '1' then
 540                 -- for the second half of a 16-byte transfer, use next_addr
 541                 addr := next_addr;
 542             end if;
 543             if l_in.mode_32bit = '1' then
 544                 addr(63 downto 32) := (others => '0');
 545             end if;
 546             v.addr := addr;
 547             maddr := l_in.addr2;    -- address from RB for tlbie
 548
 549             -- XXX Temporary hack. Mark the op as non-cachable if the address
 550             -- is the form 0xc------- for a real-mode access.
 551             if addr(31 downto 28) = "1100" and l_in.virt_mode = '0' then
 552                 v.nc := '1';
 553             end if;
 554
 555             if l_in.second = '0' then
 556                 -- Do length_to_sel and work out if we are doing 2 dwords
 557                 long_sel := xfer_data_sel(l_in.length, lsu_sum(2 downto 0));
 558                 byte_sel := long_sel(7 downto 0);
 559                 v.first_bytes := byte_sel;
 560                 v.second_bytes := long_sel(15 downto 8);
 561             else
 562                 byte_sel := r.first_bytes;
 563                 long_sel := r.second_bytes & r.first_bytes;
 564             end if;
 565
 566             -- check alignment for larx/stcx
 567             misaligned := or (std_ulogic_vector(unsigned(l_in.length(2 downto 0)) - 1) and addr(2 downto 0));
 568             v.align_intr := l_in.reserve and misaligned;
 569             if l_in.repeat = '1' and l_in.second = '0' and addr(3) = '1' then
 570                 -- length is really 16 not 8
 571                 -- Make misaligned lq cause an alignment interrupt in LE mode,
 572                 -- in order to avoid the case with RA = RT + 1 where the second half
 573                 -- faults but the first doesn't (and updates RT+1, destroying RA).
 574                 -- The equivalent BE case doesn't occur because RA = RT is illegal.
 575                 misaligned := '1';
 576                 if l_in.reserve = '1' or (l_in.op = OP_LOAD and l_in.byte_reverse = '0') then
 577                     v.align_intr := '1';
 578                 end if;
 579             end if;
 580
 581             v.atomic := not misaligned;
 582             v.atomic_last := not misaligned and (l_in.second or not l_in.repeat);
 583
 584             case l_in.op is
 585                 when OP_STORE =>
 586                     req := '1';
 587                 when OP_LOAD =>
 588                     req := '1';
 589                     v.load := '1';
 590                     -- Allow an extra cycle for RA update on loads
 591                     v.extra_cycle := l_in.update;
 592                     if HAS_FPU and l_in.is_32bit = '1' then
 593                         -- Allow an extra cycle for SP->DP precision conversion
 594                         v.load_sp := '1';
 595                         v.extra_cycle := '1';
 596                     end if;
 597                 when OP_DCBZ =>
 598                     v.align_intr := v.nc;
 599                     req := '1';
 600                     v.dcbz := '1';
 601                 when OP_TLBIE =>
 602                     mmureq := '1';
 603                     v.tlbie := '1';
 604                     v.state := TLBIE_WAIT;
 605                     v.wait_mmu := '1';
 606                 when OP_MFSPR =>
 607                     v.wr_sel := "00";
 608                     -- partial decode on SPR number should be adequate given
 609                     -- the restricted set that get sent down this path
 610                     if sprn(9) = '0' and sprn(5) = '0' then
 611                         if sprn(0) = '0' then
 612                             v.sprval := x"00000000" & r.dsisr;
 613                         else
 614                             v.sprval := r.dar;
 615                         end if;
 616                     else
 617                         -- reading one of the SPRs in the MMU
 618                         v.sprval := m_in.sprval;
 619                     end if;
 620                     v.state := COMPLETE;
 621                 when OP_MTSPR =>
 622                     if sprn(9) = '0' and sprn(5) = '0' then
 623                         if sprn(0) = '0' then
 624                             v.dsisr := l_in.data(31 downto 0);
 625                         else
 626                             v.dar := l_in.data;
 627                         end if;
 628                         v.state := COMPLETE;
 629                     else
 630                         -- writing one of the SPRs in the MMU
 631                         mmu_mtspr := '1';
 632                         v.state := TLBIE_WAIT;
 633                         v.wait_mmu := '1';
 634                     end if;
 635                 when OP_FETCH_FAILED =>
 636                     -- send it to the MMU to do the radix walk
 637                     maddr := l_in.nia;
 638                     v.instr_fault := '1';
 639                     mmureq := '1';
 640                     v.state := MMU_LOOKUP;
 641                     v.wait_mmu := '1';
 642                 when others =>
 643                     assert false report "unknown op sent to loadstore1";
 644             end case;
 645
 646             if req = '1' then
 647                 if v.align_intr = '1' then
 648                     v.state := COMPLETE;
 649                 elsif long_sel(15 downto 8) = "00000000" then
 650                     v.state := ACK_WAIT;
 651                 else
 652                     v.state := SECOND_REQ;
 653                 end if;
 654             end if;
 655
 656             v.busy := req or mmureq or mmu_mtspr;
 657         end if;
 658
 659         -- Work out controls for store formatting
 660         if l_in.valid = '1' then
 661             byte_offset := unsigned(lsu_sum(2 downto 0));
 662             byte_rev := l_in.byte_reverse;
 663             length := l_in.length;
 664             brev_lenm1 := "000";
 665             if byte_rev = '1' then
 666                 brev_lenm1 := unsigned(length(2 downto 0)) - 1;
 667             end if;
 668             v.byte_offset := byte_offset;
 669             v.brev_mask := brev_lenm1;
 670         end if;
 671
 672         -- Work out load formatter controls for next cycle
 673         byte_offset := unsigned(v.addr(2 downto 0));
 674         brev_lenm1 := "000";
 675         if v.byte_reverse = '1' then
 676             brev_lenm1 := unsigned(v.length(2 downto 0)) - 1;
 677         end if;
 678
 679         for i in 0 to 7 loop
 680             kk := ('0' & (to_unsigned(i, 3) xor brev_lenm1)) + ('0' & byte_offset);
 681             v.use_second(i) := kk(3);
 682             v.byte_index(i) := kk(2 downto 0);
 683         end loop;
 684
 685         for i in 0 to 7 loop
 686             if i < to_integer(unsigned(v.length)) then
 687                 if v.dwords_done = '1' then
 688                     v.trim_ctl(i) := '1' & not v.use_second(i);
 689                 else
 690                     v.trim_ctl(i) := "10";
 691                 end if;
 692             else
 693                 v.trim_ctl(i) := '0' & v.sign_extend;
 694             end if;
 695         end loop;
 696
 697         -- Update outputs to dcache
 698         d_out.valid <= req and not v.align_intr;
 699         d_out.load <= v.load;
 700         d_out.dcbz <= v.dcbz;
 701         d_out.nc <= v.nc;
 702         d_out.reserve <= v.reserve;
 703         d_out.atomic <= v.atomic;
 704         d_out.atomic_last <= v.atomic_last;
 705         d_out.addr <= addr;
 706         d_out.data <= store_data;
 707         d_out.byte_sel <= byte_sel;
 708         d_out.virt_mode <= v.virt_mode;
 709         d_out.priv_mode <= v.priv_mode;
 710
 711         -- Update outputs to MMU
 712         m_out.valid <= mmureq;
 713         m_out.iside <= v.instr_fault;
 714         m_out.load <= r.load;
 715         m_out.priv <= r.priv_mode;
 716         m_out.tlbie <= v.tlbie;
 717         m_out.mtspr <= mmu_mtspr;
 718         m_out.sprn <= sprn;
 719         m_out.addr <= maddr;
 720         m_out.slbia <= l_in.insn(7);
 721         m_out.rs <= l_in.data;
 722
 723         -- Update outputs to writeback
 724         -- Multiplex either cache data to the destination GPR or
 725         -- the address for the rA update.
 726         l_out.valid <= done;
 727         case r.wr_sel is
 728         when "00" =>
 729             l_out.write_enable <= '1';
 730             l_out.write_reg <= r.write_reg;
 731             l_out.write_data <= r.sprval;
 732         when "01" =>
 733             l_out.write_enable <= do_update;
 734             l_out.write_reg <= gpr_to_gspr(r.update_reg);
 735             l_out.write_data <= r.addr;
 736         when "10" =>
 737             l_out.write_enable <= '1';
 738             l_out.write_reg <= r.write_reg;
 739             l_out.write_data <= load_dp_data;
 740         when others =>
 741             l_out.write_enable <= write_enable;
 742             l_out.write_reg <= r.write_reg;
 743             l_out.write_data <= data_trimmed;
 744         end case;
 745         l_out.xerc <= r.xerc;
 746         l_out.rc <= r.rc and done;
 747         l_out.store_done <= d_in.store_done;
 748
 749         -- update exception info back to execute1
 750         e_out.busy <= busy;
 751         e_out.exception <= exception;
 752         e_out.alignment <= r.align_intr;
 753         e_out.instr_fault <= r.instr_fault;
 754         e_out.invalid <= m_in.invalid;
 755         e_out.badtree <= m_in.badtree;
 756         e_out.perm_error <= m_in.perm_error;
 757         e_out.rc_error <= m_in.rc_error;
 758         e_out.segment_fault <= m_in.segerr;
 759         if exception = '1' and r.instr_fault = '0' then
 760             v.dar := addr;
 761             if m_in.segerr = '0' and r.align_intr = '0' then
 762                 v.dsisr := dsisr;
 763             end if;
 764         end if;
 765
 766         -- Update registers
 767         rin <= v;
 768
 769     end process;
 770
 771     l1_log: if LOG_LENGTH > 0 generate
 772         signal log_data : std_ulogic_vector(9 downto 0);
 773     begin
 774         ls1_log: process(clk)
 775         begin
 776             if rising_edge(clk) then
 777                 log_data <= e_out.busy &
 778                             e_out.exception &
 779                             l_out.valid &
 780                             m_out.valid &
 781                             d_out.valid &
 782                             m_in.done &
 783                             r.dwords_done &
 784                             std_ulogic_vector(to_unsigned(state_t'pos(r.state), 3));
 785             end if;
 786         end process;
 787         log_out <= log_data;
 788     end generate;
 789
 790 end;