sort out build of chip/corona using experiments10_verilog
[soc-cocotb-sim.git] / ls180 / post_pnr / cocotb / Makefile
1 CURDIR=$(realpath .)
2 TOPDIR=$(realpath ..)
3
4 ifeq ($(PYTHONPATH),)
5 PYTHONPATH := $(TOPDIR)
6 else
7 PYTHONPATH := $(TOPDIR):$(PYTHONPATH)
8 endif
9 export PYTHONPATH
10
11 VSTDIR=$(TOPDIR)/vst_src
12 #CHIPDIR=$(TOPDIR)/chip_corona
13 NSXLIBDIR=$(TOPDIR)/nsxlib
14 NIOLIBDIR=$(TOPDIR)/niolib
15 # $(CHIPDIR)/chip_r.vhd
16 # $(CHIPDIR)/corona_cts_r.vhd
17 VHDL_SOURCES = \
18 $(wildcard $(VSTDIR)/*.vst) \
19 $(wildcard $(NSXLIBDIR)/*.vhd) \
20 $(wildcard $(NIOLIBDIR)/*.vhd)
21 TOPLEVEL=chip
22 TOPLEVEL_LANG=vhdl
23 MODULE ?= test
24 SIM=ghdl
25 GPI_IMPL=vhpi
26 GHDL_ARGS=--std=08
27 SIM_ARGS?=--vcd=test.vcd
28
29 COCOTBMAKEFILESDIR=$(shell cocotb-config --makefiles)
30
31 include $(COCOTBMAKEFILESDIR)/Makefile.sim