sort out build of chip/corona using experiments10_verilog

diff --git a/ls180/post_pnr/cocotb/Makefile b/ls180/post_pnr/cocotb/Makefile
index a53c81bd318903f679b4d2a3788956ae84bb6e73..bf1bfcf51720db6d6449aa766707fe522ce5f570 100644 (file)
--- a/ls180/post_pnr/cocotb/Makefile
+++ b/ls180/post_pnr/cocotb/Makefile
@@ -9,7 +9,7 @@ endif
 export PYTHONPATH
 
 VSTDIR=$(TOPDIR)/vst_src
-CHIPDIR=$(TOPDIR)/chip_corona
+#CHIPDIR=$(TOPDIR)/chip_corona
 NSXLIBDIR=$(TOPDIR)/nsxlib
 NIOLIBDIR=$(TOPDIR)/niolib
 #  $(CHIPDIR)/chip_r.vhd 
@@ -18,7 +18,7 @@ VHDL_SOURCES = \
   $(wildcard $(VSTDIR)/*.vst) \
   $(wildcard $(NSXLIBDIR)/*.vhd) \
   $(wildcard $(NIOLIBDIR)/*.vhd)
-TOPLEVEL=chip_r
+TOPLEVEL=chip
 TOPLEVEL_LANG=vhdl
 MODULE ?= test
 SIM=ghdl

diff --git a/ls180/post_pnr/vhd2obj.py b/ls180/post_pnr/vhd2obj.py
index afb485aa7b363570f38b47dddf6e08237d8e8922..ce3c9b82db839f5d4fad445da2dd979fc8966c57 100755 (executable)
--- a/ls180/post_pnr/vhd2obj.py
+++ b/ls180/post_pnr/vhd2obj.py
@@ -25,8 +25,8 @@ for srcdir, suffix in SRC:
         os.system("ghdl -a -g --std=08 ../%s/%s" % (srcdir, fname))
 
 # and chip and corona
-os.system("ghdl -a -g --std=08 ../chip_corona/chip_r.vhd")
-os.system("ghdl -a -g --std=08 ../chip_corona/corona_cts_r.vhd")
+#os.system("ghdl -a -g --std=08 ../chip_corona/chip_r.vhd")
+#os.system("ghdl -a -g --std=08 ../chip_corona/corona_cts_r.vhd")
 
 # back to original dir
 os.chdir(cwd)