ls180_test/Makefile

   1
   2 YOSYS                   = yosys
   3 YOSYS_INCLUDE   = $(shell yosys-config --datdir)/include
   4
   5 all: tb
   6         ./tb
   7
   8 tb: main.cpp ls180.cpp
   9         clang++ -g -O3 -std=c++14 -I $(YOSYS_INCLUDE) $< -o $@
  10
  11 #../../soc/src/soc/litex/florent/libresoc.v \
  12 #../../soc/src/soc/litex/florent/ls180.v
  13 VERILOG_SOURCES := \
  14   ./SPBlock_512W64B8W.v \
  15   #./libresoc.v \
  16   #./ls180.v
  17
  18 ls180.cpp: $(VERILOG_SOURCES)
  19         # create dummy memory files
  20         yes 0 | head -128 > mem.init
  21         yes 0 | head -32 > mem_1.init
  22         echo $<
  23         $(YOSYS) -p "read_verilog $?; write_cxxrtl $@"
  24
  25 # build verilog from nmigen
  26 ls180.v: ls180.py
  27         python3 ls180.py
  28
  29 clean:
  30         \rm -f ls180.cpp tb ls180.v