microwatt.core

   1 CAPI=2:
   2
   3 name : ::microwatt:0
   4
   5 filesets:
   6   core:
   7     files:
   8       - decode_types.vhdl
   9       - wishbone_types.vhdl
  10       - common.vhdl
  11       - fetch1.vhdl
  12       - decode1.vhdl
  13       - helpers.vhdl
  14       - decode2.vhdl
  15       - register_file.vhdl
  16       - cr_file.vhdl
  17       - crhelpers.vhdl
  18       - ppc_fx_insns.vhdl
  19       - sim_console.vhdl
  20       - logical.vhdl
  21       - countzero.vhdl
  22       - gpr_hazard.vhdl
  23       - cr_hazard.vhdl
  24       - control.vhdl
  25       - execute1.vhdl
  26       - fpu.vhdl
  27       - loadstore1.vhdl
  28       - mmu.vhdl
  29       - dcache.vhdl
  30       - divider.vhdl
  31       - rotator.vhdl
  32       - writeback.vhdl
  33       - insn_helpers.vhdl
  34       - core.vhdl
  35       - icache.vhdl
  36       - plru.vhdl
  37       - cache_ram.vhdl
  38       - core_debug.vhdl
  39       - utils.vhdl
  40     file_type : vhdlSource-2008
  41
  42   soc:
  43     files:
  44       - wishbone_arbiter.vhdl
  45       - wishbone_debug_master.vhdl
  46       - wishbone_bram_wrapper.vhdl
  47       - soc.vhdl
  48       - xics.vhdl
  49       - syscon.vhdl
  50       - sync_fifo.vhdl
  51       - spi_rxtx.vhdl
  52       - spi_flash_ctrl.vhdl
  53     file_type : vhdlSource-2008
  54
  55   fpga:
  56     files:
  57       - fpga/main_bram.vhdl
  58       - fpga/soc_reset.vhdl
  59       - fpga/pp_fifo.vhd
  60       - fpga/pp_soc_uart.vhd
  61       - fpga/pp_utilities.vhd
  62       - fpga/firmware.hex : {copyto : firmware.hex, file_type : user}
  63     file_type : vhdlSource-2008
  64
  65   xilinx_specific:
  66     files:
  67       - xilinx-mult.vhdl : {file_type : vhdlSource-2008}
  68       - fpga/fpga-random.vhdl : {file_type : vhdlSource-2008}
  69       - fpga/fpga-random.xdc : {file_type : xdc}
  70
  71   debug_xilinx:
  72     files:
  73       - dmi_dtm_xilinx.vhdl : {file_type : vhdlSource-2008}
  74
  75   debug_dummy:
  76     files:
  77       - dmi_dtm_dummy.vhdl : {file_type : vhdlSource-2008}
  78
  79   nexys_a7:
  80     files:
  81       - fpga/nexys_a7.xdc : {file_type : xdc}
  82       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  83       - fpga/top-generic.vhdl : {file_type : vhdlSource-2008}
  84
  85   nexys_video:
  86     files:
  87       - fpga/nexys-video.xdc : {file_type : xdc}
  88       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  89       - fpga/top-nexys-video.vhdl : {file_type : vhdlSource-2008}
  90
  91   acorn_cle_215:
  92     files:
  93       - fpga/acorn-cle-215.xdc : {file_type : xdc}
  94       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  95       - fpga/top-acorn-cle-215.vhdl : {file_type : vhdlSource-2008}
  96
  97   genesys2:
  98     files:
  99       - fpga/genesys2.xdc : {file_type : xdc}
 100       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
 101       - fpga/top-genesys2.vhdl : {file_type : vhdlSource-2008}
 102
 103   arty_a7:
 104     files:
 105       - fpga/arty_a7.xdc : {file_type : xdc}
 106       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
 107       - fpga/top-arty.vhdl : {file_type : vhdlSource-2008}
 108
 109   cmod_a7-35:
 110     files:
 111       - fpga/cmod_a7-35.xdc : {file_type : xdc}
 112       - fpga/clk_gen_mcmm.vhd : {file_type : vhdlSource-2008}
 113       - fpga/top-generic.vhdl : {file_type : vhdlSource-2008}
 114
 115   litedram:
 116       depend : [":microwatt:litedram"]
 117
 118   liteeth:
 119       depend : [":microwatt:liteeth"]
 120
 121   uart16550:
 122       depend : ["::uart16550"]
 123
 124 targets:
 125   nexys_a7:
 126     default_tool: vivado
 127     filesets: [core, nexys_a7, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
 128     parameters :
 129       - memory_size
 130       - ram_init_file
 131       - clk_input
 132       - clk_frequency
 133       - disable_flatten_core
 134       - log_length=2048
 135       - uart_is_16550
 136       - has_fpu
 137     tools:
 138       vivado: {part : xc7a100tcsg324-1}
 139     toplevel : toplevel
 140
 141   acorn-cle-215-nodram:
 142     default_tool: vivado
 143     filesets: [core, acorn_cle_215, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
 144     parameters :
 145       - memory_size
 146       - ram_init_file
 147       - clk_input
 148       - clk_frequency
 149       - disable_flatten_core
 150       - spi_flash_offset=10485760
 151       - log_length=2048
 152       - uart_is_16550
 153     tools:
 154       vivado: {part : xc7a200tsbg484-2}
 155     toplevel : toplevel
 156
 157   genesys2-nodram:
 158     default_tool: vivado
 159     filesets: [core, genesys2, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
 160     parameters :
 161       - memory_size
 162       - ram_init_file
 163       - clk_frequency
 164       - use_litedram=false
 165       - no_bram=false
 166       - disable_flatten_core
 167       - spi_flash_offset=10485760
 168       - log_length=2048
 169       - uart_is_16550=false
 170     tools:
 171       vivado: {part : xc7k325tffg900-2}
 172     toplevel : toplevel
 173
 174   acorn-cle-215:
 175     default_tool: vivado
 176     filesets: [core, acorn_cle_215, soc, fpga, debug_xilinx, litedram, uart16550, xilinx_specific]
 177     parameters :
 178       - memory_size
 179       - ram_init_file
 180       - use_litedram=true
 181       - disable_flatten_core
 182       - no_bram
 183       - spi_flash_offset=10485760
 184       - log_length=2048
 185       - uart_is_16550
 186     generate: [litedram_acorn_cle_215]
 187     tools:
 188       vivado: {part : xc7a200tsbg484-2}
 189     toplevel : toplevel
 190
 191   genesys2:
 192     default_tool: vivado
 193     filesets: [core, genesys2, soc, fpga, debug_xilinx, litedram, uart16550, xilinx_specific]
 194     parameters :
 195       - memory_size
 196       - ram_init_file
 197       - use_litedram=true
 198       - disable_flatten_core
 199       - no_bram
 200       - spi_flash_offset=10485760
 201       - log_length=2048
 202       - uart_is_16550=false
 203     generate: [litedram_genesys2]
 204     tools:
 205       vivado: {part : xc7k325tffg900-2}
 206     toplevel : toplevel
 207
 208   nexys_video-nodram:
 209     default_tool: vivado
 210     filesets: [core, nexys_video, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
 211     parameters :
 212       - memory_size
 213       - ram_init_file
 214       - clk_input
 215       - clk_frequency
 216       - disable_flatten_core
 217       - spi_flash_offset=10485760
 218       - log_length=2048
 219       - uart_is_16550
 220       - has_fpu
 221     tools:
 222       vivado: {part : xc7a200tsbg484-1}
 223     toplevel : toplevel
 224
 225   nexys_video:
 226     default_tool: vivado
 227     filesets: [core, nexys_video, soc, fpga, debug_xilinx, litedram, uart16550, xilinx_specific]
 228     parameters:
 229       - memory_size
 230       - ram_init_file
 231       - use_litedram=true
 232       - disable_flatten_core
 233       - no_bram
 234       - spi_flash_offset=10485760
 235       - log_length=2048
 236       - uart_is_16550
 237       - has_fpu
 238     generate: [litedram_nexys_video]
 239     tools:
 240       vivado: {part : xc7a200tsbg484-1}
 241     toplevel : toplevel
 242
 243   arty_a7-35-nodram:
 244     default_tool: vivado
 245     filesets: [core, arty_a7, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
 246     parameters :
 247       - memory_size
 248       - ram_init_file
 249       - clk_input
 250       - clk_frequency
 251       - disable_flatten_core
 252       - spi_flash_offset=3145728
 253       - log_length=512
 254       - uart_is_16550
 255       - has_uart1
 256       - has_fpu=false
 257     tools:
 258       vivado: {part : xc7a35ticsg324-1L}
 259     toplevel : toplevel
 260
 261   arty_a7-35:
 262     default_tool: vivado
 263     filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram, liteeth, uart16550, xilinx_specific]
 264     parameters :
 265       - memory_size
 266       - ram_init_file
 267       - use_litedram=true
 268       - use_liteeth=true
 269       - disable_flatten_core
 270       - no_bram
 271       - spi_flash_offset=3145728
 272       - log_length=512
 273       - uart_is_16550
 274       - has_uart1
 275       - has_fpu=false
 276     generate: [litedram_arty, liteeth_arty]
 277     tools:
 278       vivado: {part : xc7a35ticsg324-1L}
 279     toplevel : toplevel
 280
 281   arty_a7-100-nodram:
 282     default_tool: vivado
 283     filesets: [core, arty_a7, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
 284     parameters :
 285       - memory_size
 286       - ram_init_file
 287       - clk_input
 288       - clk_frequency
 289       - disable_flatten_core
 290       - spi_flash_offset=4194304
 291       - log_length=2048
 292       - uart_is_16550
 293       - has_uart1
 294       - has_fpu
 295     tools:
 296       vivado: {part : xc7a100ticsg324-1L}
 297     toplevel : toplevel
 298
 299   arty_a7-100:
 300     default_tool: vivado
 301     filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram, liteeth, uart16550, xilinx_specific]
 302     parameters:
 303       - memory_size
 304       - ram_init_file
 305       - use_litedram=true
 306       - use_liteeth=true
 307       - disable_flatten_core
 308       - no_bram
 309       - spi_flash_offset=4194304
 310       - log_length=2048
 311       - uart_is_16550
 312       - has_uart1
 313       - has_fpu
 314     generate: [litedram_arty, liteeth_arty]
 315     tools:
 316       vivado: {part : xc7a100ticsg324-1L}
 317     toplevel : toplevel
 318
 319   cmod_a7-35:
 320     default_tool: vivado
 321     filesets: [core, cmod_a7-35, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
 322     parameters :
 323       - memory_size
 324       - ram_init_file
 325       - reset_low=false
 326       - clk_input=12000000
 327       - clk_frequency
 328       - disable_flatten_core
 329       - log_length=512
 330       - uart_is_16550
 331       - has_fpu=false
 332     tools:
 333       vivado: {part : xc7a35tcpg236-1}
 334     toplevel : toplevel
 335
 336   synth:
 337     filesets: [core, soc, xilinx_specific]
 338     tools:
 339       vivado: {pnr : none}
 340     toplevel: core
 341
 342 generate:
 343   litedram_arty:
 344     generator: litedram_gen
 345     parameters: {board : arty}
 346
 347   liteeth_arty:
 348     generator: liteeth_gen
 349     parameters: {board : arty}
 350
 351   litedram_nexys_video:
 352     generator: litedram_gen
 353     parameters: {board : nexys-video}
 354
 355   litedram_acorn_cle_215:
 356     generator: litedram_gen
 357     parameters: {board : acorn-cle-215}
 358
 359   litedram_genesys2:
 360     generator: litedram_gen
 361     parameters: {board : genesys2}
 362
 363 parameters:
 364   memory_size:
 365     datatype    : int
 366     description : On-chip memory size (bytes). If no_bram is set, this is the size carved out for the DRAM payload
 367     paramtype   : generic
 368     default     : 16384
 369
 370   ram_init_file:
 371     datatype    : file
 372     description : Initial on-chip RAM contents
 373     paramtype   : generic
 374
 375   reset_low:
 376     datatype    : bool
 377     description : External reset button polarity
 378     paramtype   : generic
 379
 380   clk_input:
 381     datatype    : int
 382     description : Clock input frequency in HZ (for top-generic based boards)
 383     paramtype   : generic
 384     default     : 100000000
 385
 386   clk_frequency:
 387     datatype    : int
 388     description : Generated system clock frequency in HZ (for top-generic based boards)
 389     paramtype   : generic
 390     default     : 100000000
 391
 392   has_fpu:
 393     datatype    : bool
 394     description : Include a floating-point unit in the core
 395     paramtype   : generic
 396     default     : true
 397
 398   disable_flatten_core:
 399     datatype    : bool
 400     description : Prevent Vivado from flattening the main core components
 401     paramtype   : generic
 402     default     : false
 403
 404   use_litedram:
 405     datatype    : bool
 406     description : Use liteDRAM
 407     paramtype   : generic
 408     default     : false
 409
 410   use_liteeth:
 411     datatype    : bool
 412     description : Use liteEth
 413     paramtype   : generic
 414     default     : false
 415
 416   uart_is_16550:
 417     datatype    : bool
 418     description : Use 16550-compatible UART from OpenCores
 419     paramtype   : generic
 420     default     : true
 421
 422   has_uart1:
 423     datatype    : bool
 424     description : Enable second UART (always 16550-compatible)
 425     paramtype   : generic
 426     default     : false
 427
 428   no_bram:
 429     datatype    : bool
 430     description : No internal block RAM (only DRAM and init code carrying payload)
 431     paramtype   : generic
 432     default     : false
 433
 434   spi_flash_offset:
 435     datatype    : int
 436     description : Offset (in bytes) in the SPI flash of the code payload to run
 437     paramtype   : generic
 438
 439   log_length:
 440     datatype    : int
 441     description : Length of the core log buffer in entries (32 bytes each)
 442     paramtype   : generic