nmigen/vendor/xilinx_7series.py

   1 from abc import abstractproperty
   2
   3 from ..hdl import *
   4 from ..lib.cdc import ResetSynchronizer
   5 from ..build import *
   6
   7
   8 __all__ = ["Xilinx7SeriesPlatform"]
   9
  10
  11 class Xilinx7SeriesPlatform(TemplatedPlatform):
  12     """
  13     Required tools:
  14         * ``vivado``
  15
  16     The environment is populated by running the script specified in the environment variable
  17     ``NMIGEN_ENV_Vivado``, if present.
  18
  19     Available overrides:
  20         * ``script_after_read``: inserts commands after ``read_xdc`` in Tcl script.
  21         * ``script_after_synth``: inserts commands after ``synth_design`` in Tcl script.
  22         * ``script_after_place``: inserts commands after ``place_design`` in Tcl script.
  23         * ``script_after_route``: inserts commands after ``route_design`` in Tcl script.
  24         * ``script_before_bitstream``: inserts commands before ``write_bitstream`` in Tcl script.
  25         * ``script_after_bitstream``: inserts commands after ``write_bitstream`` in Tcl script.
  26         * ``add_constraints``: inserts commands in XDC file.
  27         * ``vivado_opts``: adds extra options for ``vivado``.
  28
  29     Build products:
  30         * ``{{name}}.log``: Vivado log.
  31         * ``{{name}}_timing_synth.rpt``: Vivado report.
  32         * ``{{name}}_utilization_hierarchical_synth.rpt``: Vivado report.
  33         * ``{{name}}_utilization_synth.rpt``: Vivado report.
  34         * ``{{name}}_utilization_hierarchical_place.rpt``: Vivado report.
  35         * ``{{name}}_utilization_place.rpt``: Vivado report.
  36         * ``{{name}}_io.rpt``: Vivado report.
  37         * ``{{name}}_control_sets.rpt``: Vivado report.
  38         * ``{{name}}_clock_utilization.rpt``:  Vivado report.
  39         * ``{{name}}_route_status.rpt``: Vivado report.
  40         * ``{{name}}_drc.rpt``: Vivado report.
  41         * ``{{name}}_methodology.rpt``: Vivado report.
  42         * ``{{name}}_timing.rpt``: Vivado report.
  43         * ``{{name}}_power.rpt``: Vivado report.
  44         * ``{{name}}_route.dcp``: Vivado design checkpoint.
  45         * ``{{name}}.bit``: binary bitstream with metadata.
  46         * ``{{name}}.bin``: binary bitstream.
  47     """
  48
  49     toolchain = "Vivado"
  50
  51     device  = abstractproperty()
  52     package = abstractproperty()
  53     speed   = abstractproperty()
  54
  55     required_tools = ["vivado"]
  56     file_templates = {
  57         **TemplatedPlatform.build_script_templates,
  58         "build_{{name}}.sh": r"""
  59             # {{autogenerated}}
  60             set -e{{verbose("x")}}
  61             if [ -z "$BASH" ] ; then exec /bin/bash "$0" "$@"; fi
  62             [ -n "${{platform._toolchain_env_var}}" ] && . "${{platform._toolchain_env_var}}"
  63             {{emit_commands("sh")}}
  64         """,
  65         "{{name}}.v": r"""
  66             /* {{autogenerated}} */
  67             {{emit_verilog()}}
  68         """,
  69         "{{name}}.debug.v": r"""
  70             /* {{autogenerated}} */
  71             {{emit_debug_verilog()}}
  72         """,
  73         "{{name}}.tcl": r"""
  74             # {{autogenerated}}
  75             create_project -force -name {{name}} -part {{platform.device}}{{platform.package}}-{{platform.speed}}
  76             {% for file in platform.iter_extra_files(".v", ".sv", ".vhd", ".vhdl") -%}
  77                 add_files {{file|tcl_escape}}
  78             {% endfor %}
  79             add_files {{name}}.v
  80             read_xdc {{name}}.xdc
  81             {% for file in platform.iter_extra_files(".xdc") -%}
  82                 read_xdc {{file|tcl_escape}}
  83             {% endfor %}
  84             {{get_override("script_after_read")|default("# (script_after_read placeholder)")}}
  85             synth_design -top {{name}}
  86             foreach cell [get_cells -quiet -hier -filter {nmigen.vivado.false_path == "TRUE"}] {
  87                 set_false_path -to $cell
  88             }
  89             foreach cell [get_cells -quiet -hier -filter {nmigen.vivado.max_delay != ""}] {
  90                 set clock [get_clocks -of_objects \
  91                     [all_fanin -flat -startpoints_only [get_pin $cell/D]]]
  92                 if {[llength $clock] != 0} {
  93                     set_max_delay -datapath_only -from $clock \
  94                         -to [get_cells $cell] [get_property nmigen.vivado.max_delay $cell]
  95                 }
  96             }
  97             {{get_override("script_after_synth")|default("# (script_after_synth placeholder)")}}
  98             report_timing_summary -file {{name}}_timing_synth.rpt
  99             report_utilization -hierarchical -file {{name}}_utilization_hierachical_synth.rpt
 100             report_utilization -file {{name}}_utilization_synth.rpt
 101             opt_design
 102             place_design
 103             {{get_override("script_after_place")|default("# (script_after_place placeholder)")}}
 104             report_utilization -hierarchical -file {{name}}_utilization_hierarchical_place.rpt
 105             report_utilization -file {{name}}_utilization_place.rpt
 106             report_io -file {{name}}_io.rpt
 107             report_control_sets -verbose -file {{name}}_control_sets.rpt
 108             report_clock_utilization -file {{name}}_clock_utilization.rpt
 109             route_design
 110             {{get_override("script_after_route")|default("# (script_after_route placeholder)")}}
 111             phys_opt_design
 112             report_timing_summary -no_header -no_detailed_paths
 113             write_checkpoint -force {{name}}_route.dcp
 114             report_route_status -file {{name}}_route_status.rpt
 115             report_drc -file {{name}}_drc.rpt
 116             report_methodology -file {{name}}_methodology.rpt
 117             report_timing_summary -datasheet -max_paths 10 -file {{name}}_timing.rpt
 118             report_power -file {{name}}_power.rpt
 119             {{get_override("script_before_bitstream")|default("# (script_before_bitstream placeholder)")}}
 120             write_bitstream -force -bin_file {{name}}.bit
 121             {{get_override("script_after_bitstream")|default("# (script_after_bitstream placeholder)")}}
 122             quit
 123         """,
 124         "{{name}}.xdc": r"""
 125             # {{autogenerated}}
 126             {% for port_name, pin_name, attrs in platform.iter_port_constraints_bits() -%}
 127                 set_property LOC {{pin_name}} [get_ports {{port_name|tcl_escape}}]
 128                 {% for attr_name, attr_value in attrs.items() -%}
 129                     set_property {{attr_name}} {{attr_value|tcl_escape}} [get_ports {{port_name|tcl_escape}}]
 130                 {% endfor %}
 131             {% endfor %}
 132             {% for net_signal, port_signal, frequency in platform.iter_clock_constraints() -%}
 133                 {% if port_signal is not none -%}
 134                     create_clock -name {{port_signal.name|ascii_escape}} -period {{1000000000/frequency}} [get_ports {{port_signal.name|tcl_escape}}]
 135                 {% else -%}
 136                     create_clock -name {{net_signal.name|ascii_escape}} -period {{1000000000/frequency}} [get_nets {{net_signal|hierarchy("/")|tcl_escape}}]
 137                 {% endif %}
 138             {% endfor %}
 139             {{get_override("add_constraints")|default("# (add_constraints placeholder)")}}
 140         """
 141     }
 142     command_templates = [
 143         r"""
 144         {{invoke_tool("vivado")}}
 145             {{verbose("-verbose")}}
 146             {{get_override("vivado_opts")|options}}
 147             -mode batch
 148             -log {{name}}.log
 149             -source {{name}}.tcl
 150         """
 151     ]
 152
 153     def create_missing_domain(self, name):
 154         # Xilinx devices have a global write enable (GWE) signal that asserted during configuraiton
 155         # and deasserted once it ends. Because it is an asynchronous signal (GWE is driven by logic
 156         # syncronous to configuration clock, which is not used by most designs), even though it is
 157         # a low-skew global network, its deassertion may violate a setup/hold constraint with
 158         # relation to a user clock. The recommended solution is to use a BUFGCE driven by the EOS
 159         # signal. For details, see:
 160         #   * https://www.xilinx.com/support/answers/44174.html
 161         #   * https://www.xilinx.com/support/documentation/white_papers/wp272.pdf
 162         if name == "sync" and self.default_clk is not None:
 163             clk_i = self.request(self.default_clk).i
 164             if self.default_rst is not None:
 165                 rst_i = self.request(self.default_rst).i
 166
 167             m = Module()
 168             ready = Signal()
 169             m.submodules += Instance("STARTUPE2", o_EOS=ready)
 170             m.domains += ClockDomain("sync", reset_less=self.default_rst is None)
 171             m.submodules += Instance("BUFGCE",
 172                 p_SIM_DEVICE="7SERIES",
 173                 i_CE=ready,
 174                 i_I=clk_i,
 175                 o_O=ClockSignal("sync")
 176             )
 177             if self.default_rst is not None:
 178                 m.submodules.reset_sync = ResetSynchronizer(rst_i, domain="sync")
 179             return m
 180
 181     def add_clock_constraint(self, clock, frequency):
 182         super().add_clock_constraint(clock, frequency)
 183         clock.attrs["keep"] = "TRUE"
 184
 185     def _get_xdr_buffer(self, m, pin, *, i_invert=False, o_invert=False):
 186         def get_dff(clk, d, q):
 187             # SDR I/O is performed by packing a flip-flop into the pad IOB.
 188             for bit in range(len(q)):
 189                 m.submodules += Instance("FDCE",
 190                     a_IOB="TRUE",
 191                     i_C=clk,
 192                     i_CE=Const(1),
 193                     i_CLR=Const(0),
 194                     i_D=d[bit],
 195                     o_Q=q[bit]
 196                 )
 197
 198         def get_iddr(clk, d, q1, q2):
 199             for bit in range(len(q1)):
 200                 m.submodules += Instance("IDDR",
 201                     p_DDR_CLK_EDGE="SAME_EDGE_PIPELINED",
 202                     p_SRTYPE="ASYNC",
 203                     p_INIT_Q1=0, p_INIT_Q2=0,
 204                     i_C=clk,
 205                     i_CE=Const(1),
 206                     i_S=Const(0), i_R=Const(0),
 207                     i_D=d[bit],
 208                     o_Q1=q1[bit], o_Q2=q2[bit]
 209                 )
 210
 211         def get_oddr(clk, d1, d2, q):
 212             for bit in range(len(q)):
 213                 m.submodules += Instance("ODDR",
 214                     p_DDR_CLK_EDGE="SAME_EDGE",
 215                     p_SRTYPE="ASYNC",
 216                     p_INIT=0,
 217                     i_C=clk,
 218                     i_CE=Const(1),
 219                     i_S=Const(0), i_R=Const(0),
 220                     i_D1=d1[bit], i_D2=d2[bit],
 221                     o_Q=q[bit]
 222                 )
 223
 224         def get_ineg(y, invert):
 225             if invert:
 226                 a = Signal.like(y, name_suffix="_n")
 227                 m.d.comb += y.eq(~a)
 228                 return a
 229             else:
 230                 return y
 231
 232         def get_oneg(a, invert):
 233             if invert:
 234                 y = Signal.like(a, name_suffix="_n")
 235                 m.d.comb += y.eq(~a)
 236                 return y
 237             else:
 238                 return a
 239
 240         if "i" in pin.dir:
 241             if pin.xdr < 2:
 242                 pin_i  = get_ineg(pin.i,  i_invert)
 243             elif pin.xdr == 2:
 244                 pin_i0 = get_ineg(pin.i0, i_invert)
 245                 pin_i1 = get_ineg(pin.i1, i_invert)
 246         if "o" in pin.dir:
 247             if pin.xdr < 2:
 248                 pin_o  = get_oneg(pin.o,  o_invert)
 249             elif pin.xdr == 2:
 250                 pin_o0 = get_oneg(pin.o0, o_invert)
 251                 pin_o1 = get_oneg(pin.o1, o_invert)
 252
 253         i = o = t = None
 254         if "i" in pin.dir:
 255             i = Signal(pin.width, name="{}_xdr_i".format(pin.name))
 256         if "o" in pin.dir:
 257             o = Signal(pin.width, name="{}_xdr_o".format(pin.name))
 258         if pin.dir in ("oe", "io"):
 259             t = Signal(1,         name="{}_xdr_t".format(pin.name))
 260
 261         if pin.xdr == 0:
 262             if "i" in pin.dir:
 263                 i = pin_i
 264             if "o" in pin.dir:
 265                 o = pin_o
 266             if pin.dir in ("oe", "io"):
 267                 t = ~pin.oe
 268         elif pin.xdr == 1:
 269             if "i" in pin.dir:
 270                 get_dff(pin.i_clk, i, pin_i)
 271             if "o" in pin.dir:
 272                 get_dff(pin.o_clk, pin_o, o)
 273             if pin.dir in ("oe", "io"):
 274                 get_dff(pin.o_clk, ~pin.oe, t)
 275         elif pin.xdr == 2:
 276             if "i" in pin.dir:
 277                 get_iddr(pin.i_clk, i, pin_i0, pin_i1)
 278             if "o" in pin.dir:
 279                 get_oddr(pin.o_clk, pin_o0, pin_o1, o)
 280             if pin.dir in ("oe", "io"):
 281                 get_dff(pin.o_clk, ~pin.oe, t)
 282         else:
 283             assert False
 284
 285         return (i, o, t)
 286
 287     def get_input(self, pin, port, attrs, invert):
 288         self._check_feature("single-ended input", pin, attrs,
 289                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 290         m = Module()
 291         i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert)
 292         for bit in range(len(port)):
 293             m.submodules["{}_{}".format(pin.name, bit)] = Instance("IBUF",
 294                 i_I=port[bit],
 295                 o_O=i[bit]
 296             )
 297         return m
 298
 299     def get_output(self, pin, port, attrs, invert):
 300         self._check_feature("single-ended output", pin, attrs,
 301                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 302         m = Module()
 303         i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
 304         for bit in range(len(port)):
 305             m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBUF",
 306                 i_I=o[bit],
 307                 o_O=port[bit]
 308             )
 309         return m
 310
 311     def get_tristate(self, pin, port, attrs, invert):
 312         self._check_feature("single-ended tristate", pin, attrs,
 313                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 314         m = Module()
 315         i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
 316         for bit in range(len(port)):
 317             m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBUFT",
 318                 i_T=t,
 319                 i_I=o[bit],
 320                 o_O=port[bit]
 321             )
 322         return m
 323
 324     def get_input_output(self, pin, port, attrs, invert):
 325         self._check_feature("single-ended input/output", pin, attrs,
 326                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 327         m = Module()
 328         i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert, o_invert=invert)
 329         for bit in range(len(port)):
 330             m.submodules["{}_{}".format(pin.name, bit)] = Instance("IOBUF",
 331                 i_T=t,
 332                 i_I=o[bit],
 333                 o_O=i[bit],
 334                 io_IO=port[bit]
 335             )
 336         return m
 337
 338     def get_diff_input(self, pin, p_port, n_port, attrs, invert):
 339         self._check_feature("differential input", pin, attrs,
 340                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 341         m = Module()
 342         i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert)
 343         for bit in range(len(p_port)):
 344             m.submodules["{}_{}".format(pin.name, bit)] = Instance("IBUFDS",
 345                 i_I=p_port[bit], i_IB=n_port[bit],
 346                 o_O=i[bit]
 347             )
 348         return m
 349
 350     def get_diff_output(self, pin, p_port, n_port, attrs, invert):
 351         self._check_feature("differential output", pin, attrs,
 352                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 353         m = Module()
 354         i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
 355         for bit in range(len(p_port)):
 356             m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBUFDS",
 357                 i_I=o[bit],
 358                 o_O=p_port[bit], o_OB=n_port[bit]
 359             )
 360         return m
 361
 362     def get_diff_tristate(self, pin, p_port, n_port, attrs, invert):
 363         self._check_feature("differential tristate", pin, attrs,
 364                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 365         m = Module()
 366         i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
 367         for bit in range(len(p_port)):
 368             m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBUFTDS",
 369                 i_T=t,
 370                 i_I=o[bit],
 371                 o_O=p_port[bit], o_OB=n_port[bit]
 372             )
 373         return m
 374
 375     def get_diff_input_output(self, pin, p_port, n_port, attrs, invert):
 376         self._check_feature("differential input/output", pin, attrs,
 377                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 378         m = Module()
 379         i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert, o_invert=invert)
 380         for bit in range(len(p_port)):
 381             m.submodules["{}_{}".format(pin.name, bit)] = Instance("IOBUFDS",
 382                 i_T=t,
 383                 i_I=o[bit],
 384                 o_O=i[bit],
 385                 io_IO=p_port[bit], io_IOB=n_port[bit]
 386             )
 387         return m
 388
 389     # The synchronizer implementations below apply two separate but related timing constraints.
 390     #
 391     # First, the ASYNC_REG attribute prevents inference of shift registers from synchronizer FFs,
 392     # and constraints the FFs to be placed as close as possible, ideally in one CLB. This attribute
 393     # only affects the synchronizer FFs themselves.
 394     #
 395     # Second, the nmigen.vivado.false_path or nmigen.vivado.max_delay attribute affects the path
 396     # into the synchronizer. If maximum input delay is specified, a datapath-only maximum delay
 397     # constraint is applied, limiting routing delay (and therefore skew) at the synchronizer input.
 398     # Otherwise, a false path constraint is used to omit the input path from the timing analysis.
 399
 400     def get_ff_sync(self, ff_sync):
 401         m = Module()
 402         flops = [Signal(ff_sync.i.shape(), name="stage{}".format(index),
 403                         reset=ff_sync._reset, reset_less=ff_sync._reset_less,
 404                         attrs={"ASYNC_REG": "TRUE"})
 405                  for index in range(ff_sync._stages)]
 406         if ff_sync._max_input_delay is None:
 407             flops[0].attrs["nmigen.vivado.false_path"] = "TRUE"
 408         else:
 409             flops[0].attrs["nmigen.vivado.max_delay"] = str(ff_sync._max_input_delay * 1e9)
 410         for i, o in zip((ff_sync.i, *flops), flops):
 411             m.d[ff_sync._o_domain] += o.eq(i)
 412         m.d.comb += ff_sync.o.eq(flops[-1])
 413         return m
 414
 415     def get_async_ff_sync(self, async_ff_sync):
 416         m = Module()
 417         m.domains += ClockDomain("async_ff", async_reset=True, local=True)
 418         flops = [Signal(1, name="stage{}".format(index), reset=1,
 419                         attrs={"ASYNC_REG": "TRUE"})
 420                  for index in range(async_ff_sync._stages)]
 421         if async_ff_sync._max_input_delay is None:
 422             flops[0].attrs["nmigen.vivado.false_path"] = "TRUE"
 423         else:
 424             flops[0].attrs["nmigen.vivado.max_delay"] = str(async_ff_sync._max_input_delay * 1e9)
 425         for i, o in zip((0, *flops), flops):
 426             m.d.async_ff += o.eq(i)
 427
 428         if async_ff_sync._edge == "pos":
 429             m.d.comb += ResetSignal("async_ff").eq(async_ff_sync.i)
 430         else:
 431             m.d.comb += ResetSignal("async_ff").eq(~async_ff_sync.i)
 432
 433         m.d.comb += [
 434             ClockSignal("async_ff").eq(ClockSignal(async_ff_sync._domain)),
 435             async_ff_sync.o.eq(flops[-1])
 436         ]
 437
 438         return m