Update all boards to use default_clk.
[nmigen-boards.git] / nmigen_boards / blackice.py
1 import os
2 import subprocess
3
4 from nmigen.build import *
5 from nmigen.vendor.lattice_ice40 import *
6 from .dev import *
7
8
9 __all__ = ["BlackIcePlatform"]
10
11
12 class BlackIcePlatform(LatticeICE40Platform):
13 device = "iCE40HX4K"
14 package = "TQ144"
15 default_clk = "clk100"
16 resources = [
17 Resource("clk100", 0, Pins("129", dir="i"),
18 Clock(100e6), Attrs(GLOBAL="1", IO_STANDARD="SB_LVCMOS33")
19 ),
20
21 Resource("user_led", 0, Pins("71", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS33")),
22 Resource("user_led", 1, Pins("67", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS33")),
23 Resource("user_led", 2, Pins("68", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS33")),
24 Resource("user_led", 3, Pins("70", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS33")),
25 # Color aliases
26 Resource("user_ledb", 0, Pins("71", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS33")),
27 Resource("user_ledg", 0, Pins("67", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS33")),
28 Resource("user_ledo", 0, Pins("68", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS33")),
29 Resource("user_ledr", 0, Pins("70", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS33")),
30
31 Resource("user_btn", 0, PinsN("63", dir="i"), Attrs(IO_STANDARD="SB_LVCMOS33")),
32 Resource("user_btn", 1, PinsN("64", dir="i"), Attrs(IO_STANDARD="SB_LVCMOS33")),
33
34 Resource("user_sw", 0, PinsN("37", dir="i"), Attrs(IO_STANDARD="SB_LVCMOS33")),
35 Resource("user_sw", 1, PinsN("38", dir="i"), Attrs(IO_STANDARD="SB_LVCMOS33")),
36 Resource("user_sw", 2, PinsN("39", dir="i"), Attrs(IO_STANDARD="SB_LVCMOS33")),
37 Resource("user_sw", 3, PinsN("41", dir="i"), Attrs(IO_STANDARD="SB_LVCMOS33")),
38
39 UARTResource(0,
40 rx="88", tx="85", rts="91", cts="94",
41 attrs=Attrs(IO_STANDARD="SB_LVCMOS33", PULLUP="1")
42 ),
43
44 Resource("sram", 0,
45 Subsignal("address", Pins(
46 "137 138 139 141 142 42 43 44 73 74 75 76 115 116 117 118 119 78",
47 dir="o"
48 )),
49 Subsignal("data", Pins(
50 "135 134 130 128 125 124 122 121 61 60 56 55 52 49 48 47",
51 dir="io"
52 )),
53 Subsignal("oe", PinsN("45", dir="o")),
54 Subsignal("we", PinsN("120", dir="o")),
55 Subsignal("cs", PinsN("136", dir="o")),
56 Attrs(IO_STANDARD="SB_LVCMOS33"),
57 ),
58 ]
59 connectors = [
60 Connector("pmod", 0, " 94 91 88 85 - - 95 93 90 87 - -"), # PMOD1/2
61 Connector("pmod", 1, "105 102 99 97 - - 104 101 98 96 - -"), # PMOD3/4
62 Connector("pmod", 2, "143 114 112 107 - - 144 113 110 106 - -"), # PMOD5/6
63 Connector("pmod", 3, " 10 9 2 1 - - 8 7 4 3 - -"), # PMOD7/8
64 Connector("pmod", 4, " 20 19 16 15 - - 18 17 12 11 - -"), # PMOD9/10
65 Connector("pmod", 5, " 34 33 22 21 - - 32 31 26 25 - -"), # PMOD11/12
66 Connector("pmod", 6, " 29 28 24 23 - -"), # PMOD13
67 Connector("pmod", 7, " 71 67 68 70 - -"), # PMOD14
68 ]
69
70 def toolchain_program(self, products, name):
71 with products.extract("{}.bin".format(name)) as bitstream_filename:
72 subprocess.check_call(["cp", bitstream_filename, "/dev/ttyACM0"])
73
74
75 if __name__ == "__main__":
76 from ._blinky import build_and_program
77 build_and_program(BlackIcePlatform)