Update all boards to use default_clk.

diff --git a/nmigen_boards/_blinky.py b/nmigen_boards/_blinky.py
index b0a190e534e94409559c02cc6987d04d6fb44f1e..c04b95ff4e605b3bc526e2be89dad876c9663d22 100644 (file)
--- a/nmigen_boards/_blinky.py
+++ b/nmigen_boards/_blinky.py
@@ -5,14 +5,10 @@ from nmigen.build import ResourceError
 
 
 class Blinky(Elaboratable):
-    def __init__(self, clk_name):
-        self.clk_name = clk_name
-
     def elaborate(self, platform):
         m = Module()
 
-        clk = platform.request(self.clk_name)
-        clk_freq = platform.get_clock_constraint(clk)
+        clk = platform.request(platform.default_clk)
         m.domains.sync = ClockDomain()
         m.d.comb += ClockSignal().eq(clk.i)
 
@@ -24,6 +20,7 @@ class Blinky(Elaboratable):
                 break
         leds = Cat(led.o for led in leds)
 
+        clk_freq = platform.default_clk_frequency
         ctr = Signal(max=int(clk_freq//2), reset=int(clk_freq//2) - 1)
         with m.If(ctr == 0):
             m.d.sync += ctr.eq(ctr.reset)
@@ -34,5 +31,5 @@ class Blinky(Elaboratable):
         return m
 
 
-def build_and_program(platform_cls, clk_name, **kwargs):
-    platform_cls().build(Blinky(clk_name), do_program=True, **kwargs)
+def build_and_program(platform_cls, **kwargs):
+    platform_cls().build(Blinky(), do_program=True, **kwargs)

diff --git a/nmigen_boards/blackice.py b/nmigen_boards/blackice.py
index 591f74d8008568ba874b6956ecd3a295cad4d9dc..2ec16a1dc2ea03523134070ce1390efffc3186f0 100644 (file)
--- a/nmigen_boards/blackice.py
+++ b/nmigen_boards/blackice.py
@@ -10,9 +10,10 @@ __all__ = ["BlackIcePlatform"]
 
 
 class BlackIcePlatform(LatticeICE40Platform):
-    device     = "iCE40HX4K"
-    package    = "TQ144"
-    resources  = [
+    device      = "iCE40HX4K"
+    package     = "TQ144"
+    default_clk = "clk100"
+    resources   = [
         Resource("clk100", 0, Pins("129", dir="i"),
             Clock(100e6), Attrs(GLOBAL="1", IO_STANDARD="SB_LVCMOS33")
         ),
@@ -55,8 +56,7 @@ class BlackIcePlatform(LatticeICE40Platform):
             Attrs(IO_STANDARD="SB_LVCMOS33"),
         ),
     ]
-
-    connectors = [
+    connectors  = [
         Connector("pmod", 0, " 94  91  88  85 - -  95  93  90  87 - -"),  # PMOD1/2
         Connector("pmod", 1, "105 102  99  97 - - 104 101  98  96 - -"),  # PMOD3/4
         Connector("pmod", 2, "143 114 112 107 - - 144 113 110 106 - -"),  # PMOD5/6
@@ -73,6 +73,5 @@ class BlackIcePlatform(LatticeICE40Platform):
 
 
 if __name__ == "__main__":
-    from ._blinky import Blinky
-    p = BlackIcePlatform()
-    p.build(Blinky("clk100"), do_program=True)
+    from ._blinky import build_and_program
+    build_and_program(BlackIcePlatform)

diff --git a/nmigen_boards/blackice_ii.py b/nmigen_boards/blackice_ii.py
index a9830bc3e3dff7beae93c6e5789101373c1ecaa0..da303a9bc55b544e3ce474672c72bfd6bcff9e73 100644 (file)
--- a/nmigen_boards/blackice_ii.py
+++ b/nmigen_boards/blackice_ii.py
@@ -10,9 +10,10 @@ __all__ = ["BlackIceIIPlatform"]
 
 
 class BlackIceIIPlatform(LatticeICE40Platform):
-    device     = "iCE40HX4K"
-    package    = "TQ144"
-    resources  = [
+    device      = "iCE40HX4K"
+    package     = "TQ144"
+    default_clk = "clk100"
+    resources   = [
         Resource("clk100", 0, Pins("129", dir="i"),
             Clock(100e6), Attrs(GLOBAL="1", IO_STANDARD="SB_LVCMOS33")
         ),
@@ -57,8 +58,7 @@ class BlackIceIIPlatform(LatticeICE40Platform):
             Attrs(IO_STANDARD="SB_LVCMOS33"),
         ),
     ]
-
-    connectors = [
+    connectors  = [
         Connector("pmod", 0, " 94  91  88  85 - -  95  93  90  87 - -"),  # PMOD1/2
         Connector("pmod", 1, "105 102  99  97 - - 104 101  98  96 - -"),  # PMOD3/4
         Connector("pmod", 2, "143 114 112 107 - - 144 113 110 106 - -"),  # PMOD5/6
@@ -75,6 +75,5 @@ class BlackIceIIPlatform(LatticeICE40Platform):
 
 
 if __name__ == "__main__":
-    from ._blinky import Blinky
-    p = BlackIceIIPlatform()
-    p.build(Blinky("clk100"), do_program=True)
+    from ._blinky import build_and_program
+    build_and_program(BlackIceIIPlatform)

diff --git a/nmigen_boards/ice40_hx1k_blink_evn.py b/nmigen_boards/ice40_hx1k_blink_evn.py
index 418c593efc08355414d2bbc6a912229ca12d9039..7ada8c844365494a3bec238425d73a3e33ca46c2 100644 (file)
--- a/nmigen_boards/ice40_hx1k_blink_evn.py
+++ b/nmigen_boards/ice40_hx1k_blink_evn.py
@@ -10,9 +10,10 @@ __all__ = ["ICE40HX1KBlinkEVNPlatform"]
 
 
 class ICE40HX1KBlinkEVNPlatform(LatticeICE40Platform):
-    device     = "iCE40HX1K"
-    package    = "VQ100"
-    resources  = [
+    device      = "iCE40HX1K"
+    package     = "VQ100"
+    default_clk = "clk3p3"
+    resources   = [
         Resource("clk3p3", 0, Pins("13", dir="i"), Clock(3.3e6),
                  Attrs(GLOBAL="1", IO_STANDARD="SB_LVCMOS33")),
 
@@ -31,7 +32,7 @@ class ICE40HX1KBlinkEVNPlatform(LatticeICE40Platform):
             attrs=Attrs(IO_STANDARD="SB_LVCMOS33")
         ),
     ]
-    connectors = [
+    connectors  = [
         Connector("pmod",  1, "10  9  8  7 - -  4  3  2  1 - -"), # J1
         Connector("pmod",  5, "40 42 62 64 - - 37 41 63 45 - -"), # J5
         Connector("pmod",  6, "25 24 21 20 - - 26 27 28 33 - -"), # J6
@@ -47,4 +48,4 @@ class ICE40HX1KBlinkEVNPlatform(LatticeICE40Platform):
 
 if __name__ == "__main__":
     from ._blinky import build_and_program
-    build_and_program(ICE40HX1KBlinkEVNPlatform, "clk3p3")
+    build_and_program(ICE40HX1KBlinkEVNPlatform)

diff --git a/nmigen_boards/ice40_hx8k_b_evn.py b/nmigen_boards/ice40_hx8k_b_evn.py
index 4ff8d85ecf30378fe70efb716279a7eafa051395..39b478d8207b97a89a13dd2ce98cd882ce6dc09c 100644 (file)
--- a/nmigen_boards/ice40_hx8k_b_evn.py
+++ b/nmigen_boards/ice40_hx8k_b_evn.py
@@ -10,9 +10,10 @@ __all__ = ["ICE40HX8KBEVNPlatform"]
 
 
 class ICE40HX8KBEVNPlatform(LatticeICE40Platform):
-    device     = "iCE40HX8K"
-    package    = "CT256"
-    resources  = [
+    device      = "iCE40HX8K"
+    package     = "CT256"
+    default_clk = "clk12"
+    resources   = [
         Resource("clk12", 0, Pins("J3", dir="i"),
                  Clock(12e6), Attrs(GLOBAL="1", IO_STANDARD="SB_LVCMOS33")),
 
@@ -35,7 +36,7 @@ class ICE40HX8KBEVNPlatform(LatticeICE40Platform):
             attrs=Attrs(IO_STANDARD="SB_LVCMOS33")
         ),
     ]
-    connectors = [
+    connectors  = [
         Connector("j", 1, # J1
             "A16 -   A15 B15 B13 B14 -   -   B12 B11"
             "A11 B10 A10 C9  -   -   A9  B9  B8  A7"
@@ -67,4 +68,4 @@ class ICE40HX8KBEVNPlatform(LatticeICE40Platform):
 
 if __name__ == "__main__":
     from ._blinky import build_and_program
-    build_and_program(ICE40HX8KBEVNPlatform, "clk12")
+    build_and_program(ICE40HX8KBEVNPlatform)

diff --git a/nmigen_boards/icebreaker.py b/nmigen_boards/icebreaker.py
index 39d82d5cde32b36b8684d4f8e003093a9a0eb902..a62ecdc4b1b2b17d5731959873c80568d7436cd3 100644 (file)
--- a/nmigen_boards/icebreaker.py
+++ b/nmigen_boards/icebreaker.py
@@ -10,9 +10,10 @@ __all__ = ["ICEBreakerPlatform"]
 
 
 class ICEBreakerPlatform(LatticeICE40Platform):
-    device     = "iCE40UP5K"
-    package    = "SG48"
-    resources  = [
+    device      = "iCE40UP5K"
+    package     = "SG48"
+    default_clk = "clk12"
+    resources   = [
         Resource("clk12", 0, Pins("35", dir="i"),
                  Clock(12e6), Attrs(GLOBAL="1", IO_STANDARD="SB_LVCMOS33")),
 
@@ -85,4 +86,4 @@ if __name__ == "__main__":
     from ._blinky import Blinky
     p = ICEBreakerPlatform()
     p.add_resources(p.break_off_pmod)
-    p.build(Blinky("clk12"), do_program=True)
+    p.build(Blinky(), do_program=True)

diff --git a/nmigen_boards/icestick.py b/nmigen_boards/icestick.py
index e575aacff42f6f561a859574c67c9ee69afe3da7..bdeb11248947a549b2c814aec55800d33f06c910 100644 (file)
--- a/nmigen_boards/icestick.py
+++ b/nmigen_boards/icestick.py
@@ -11,9 +11,10 @@ __all__ = ["ICEStickPlatform"]
 
 
 class ICEStickPlatform(LatticeICE40Platform):
-    device     = "iCE40HX1K"
-    package    = "TQ144"
-    resources  = [
+    device      = "iCE40HX1K"
+    package     = "TQ144"
+    default_clk = "clk12"
+    resources   = [
         Resource("clk12", 0, Pins("21", dir="i"),
                  Clock(12e6), Attrs(GLOBAL="1", IO_STANDARD="SB_LVCMOS33")),
 
@@ -38,7 +39,7 @@ class ICEStickPlatform(LatticeICE40Platform):
             attrs=Attrs(IO_STANDARD="SB_LVCMOS33")
         ),
     ]
-    connectors = [
+    connectors  = [
         Connector("pmod", 0, "78 79 80 81 - - 87 88 90 91 - -"),  # J2
 
         Connector("j", 1, "- - 112 113 114 115 116 117 118 119"), # J1
@@ -53,4 +54,4 @@ class ICEStickPlatform(LatticeICE40Platform):
 
 if __name__ == "__main__":
     from ._blinky import build_and_program
-    build_and_program(ICEStickPlatform, "clk12")
+    build_and_program(ICEStickPlatform)

diff --git a/nmigen_boards/kc705.py b/nmigen_boards/kc705.py
index 22ba5fccbadfa5cfad15decfcc7b2ae9266ad235..91e4a5b8aab13eab070d9531568f838cc550d966 100644 (file)
--- a/nmigen_boards/kc705.py
+++ b/nmigen_boards/kc705.py
@@ -10,10 +10,11 @@ __all__ = ["KC705Platform"]
 
 
 class KC705Platform(Xilinx7SeriesPlatform):
-    device     = "xc7k325t"
-    package    = "ffg900"
-    speed      = "2"
-    resources  = [
+    device      = "xc7k325t"
+    package     = "ffg900"
+    speed       = "2"
+    default_clk = "clk156"
+    resources   = [
         Resource("clk156", 0, DiffPairs("K28", "K29", dir="i"),
                  Clock(156e6), Attrs(IOSTANDARD="LVDS_25")),
 
@@ -31,7 +32,7 @@ class KC705Platform(Xilinx7SeriesPlatform):
             attrs=Attrs(IOSTANDARD="LVCMOS33")
         ),
     ]
-    connectors = []
+    connectors  = []
 
     def toolchain_program(self, products, name):
         openocd = os.environ.get("OPENOCD", "openocd")
@@ -44,4 +45,4 @@ class KC705Platform(Xilinx7SeriesPlatform):
 
 if __name__ == "__main__":
     from ._blinky import build_and_program
-    build_and_program(KC705Platform, "clk156")
+    build_and_program(KC705Platform)

diff --git a/nmigen_boards/tinyfpga_bx.py b/nmigen_boards/tinyfpga_bx.py
index 5db90cf55fa5abbc89cc911e75ec1935b4da7d5b..5e272cb61b4563744a00c264856c0a2bd4d88fd5 100644 (file)
--- a/nmigen_boards/tinyfpga_bx.py
+++ b/nmigen_boards/tinyfpga_bx.py
@@ -10,9 +10,10 @@ __all__ = ["TinyFPGABXPlatform"]
 
 
 class TinyFPGABXPlatform(LatticeICE40Platform):
-    device     = "iCE40LP8K"
-    package    = "CM81"
-    resources  = [
+    device      = "iCE40LP8K"
+    package     = "CM81"
+    default_clk = "clk16"
+    resources   = [
         Resource("clk16", 0, Pins("B2", dir="i"),
                  Clock(16e6), Attrs(IO_STANDARD="SB_LVCMOS33")),
 
@@ -29,7 +30,7 @@ class TinyFPGABXPlatform(LatticeICE40Platform):
             cs="F7", clk="G7", mosi="G6", miso="H7", wp="H4", hold="J8",
             attrs=Attrs(IO_STANDARD="SB_LVCMOS33")),
     ]
-    connectors = [
+    connectors  = [
         Connector("gpio", 0,
             # Left side of the board
             #     1  2  3  4  5  6  7  8  9 10 11 12 13
@@ -50,4 +51,4 @@ class TinyFPGABXPlatform(LatticeICE40Platform):
 
 if __name__ == "__main__":
     from ._blinky import build_and_program
-    build_and_program(TinyFPGABXPlatform, "clk16")
+    build_and_program(TinyFPGABXPlatform)

diff --git a/nmigen_boards/versa_ecp5.py b/nmigen_boards/versa_ecp5.py
index 35b28be00e8312dc15dcb89cfe5d10fea2ad811b..4b2b9f0a1b0d757b843725d831d11e4d8d63f1d7 100644 (file)
--- a/nmigen_boards/versa_ecp5.py
+++ b/nmigen_boards/versa_ecp5.py
@@ -10,10 +10,11 @@ __all__ = ["VersaECP5Platform"]
 
 
 class VersaECP5Platform(LatticeECP5Platform):
-    device     = "LFE5UM-45F"
-    package    = "BG381"
-    speed      = "8"
-    resources  = [
+    device      = "LFE5UM-45F"
+    package     = "BG381"
+    speed       = "8"
+    default_clk = "clk100"
+    resources   = [
         Resource("rst", 0, PinsN("T1", dir="i"), Attrs(IO_TYPE="LVCMOS33")),
         Resource("clk100", 0, DiffPairs("P3", "P4", dir="i"),
                  Clock(100e6), Attrs(IO_TYPE="LVDS")),
@@ -179,4 +180,4 @@ class VersaECP5Platform(LatticeECP5Platform):
 
 if __name__ == "__main__":
     from ._blinky import build_and_program
-    build_and_program(VersaECP5Platform, "clk100")
+    build_and_program(VersaECP5Platform)

diff --git a/nmigen_boards/versa_ecp5_5g.py b/nmigen_boards/versa_ecp5_5g.py
index 75512eb04f32760878df3c547f508abb1879da62..d6441f4426cee8176c883b91cd5426c9706edeae 100644 (file)
--- a/nmigen_boards/versa_ecp5_5g.py
+++ b/nmigen_boards/versa_ecp5_5g.py
@@ -5,10 +5,10 @@ __all__ = ["VersaECP55GPlatform"]
 
 
 class VersaECP55GPlatform(VersaECP5Platform):
-    device     = "LFE5UM5G-45F"
+    device      = "LFE5UM5G-45F"
     # Everything else is identical between 3G and 5G Versa boards.
 
 
 if __name__ == "__main__":
     from ._blinky import build_and_program
-    build_and_program(VersaECP55GPlatform, "clk100")
+    build_and_program(VersaECP55GPlatform)