Update all boards to use default_clk.
[nmigen-boards.git] / nmigen_boards / tinyfpga_bx.py
1 import os
2 import subprocess
3
4 from nmigen.build import *
5 from nmigen.vendor.lattice_ice40 import *
6 from .dev import *
7
8
9 __all__ = ["TinyFPGABXPlatform"]
10
11
12 class TinyFPGABXPlatform(LatticeICE40Platform):
13 device = "iCE40LP8K"
14 package = "CM81"
15 default_clk = "clk16"
16 resources = [
17 Resource("clk16", 0, Pins("B2", dir="i"),
18 Clock(16e6), Attrs(IO_STANDARD="SB_LVCMOS33")),
19
20 Resource("user_led", 0, Pins("B3", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS33")),
21
22 Resource("usb", 0,
23 Subsignal("d_p", Pins("B4", dir="io")),
24 Subsignal("d_n", Pins("A4", dir="io")),
25 Subsignal("pullup", Pins("A3", dir="o")),
26 Attrs(IO_STANDARD="SB_LVCMOS33")
27 ),
28
29 *SPIFlashResources(0,
30 cs="F7", clk="G7", mosi="G6", miso="H7", wp="H4", hold="J8",
31 attrs=Attrs(IO_STANDARD="SB_LVCMOS33")),
32 ]
33 connectors = [
34 Connector("gpio", 0,
35 # Left side of the board
36 # 1 2 3 4 5 6 7 8 9 10 11 12 13
37 " A2 A1 B1 C2 C1 D2 D1 E2 E1 G2 H1 J1 H2"
38 # Right side of the board
39 # 14 15 16 17 18 19 20 21 22 23 24
40 " H9 D9 D8 B8 A9 B8 A8 B7 A7 B6 A6"
41 # Bottom of the board
42 # 25 26 27 28 29 30 31
43 "G1 J3 J4 G9 J9 E8 J2"),
44 ]
45
46 def toolchain_program(self, products, name):
47 tinyprog = os.environ.get("TINYPROG", "tinyprog")
48 with products.extract("{}.bin".format(name)) as bitstream_filename:
49 subprocess.check_call([tinyprog, "-p", bitstream_filename])
50
51
52 if __name__ == "__main__":
53 from ._blinky import build_and_program
54 build_and_program(TinyFPGABXPlatform)