Add debug_module bus device.
[riscv-isa-sim.git] / riscv / devices.h
1 #ifndef _RISCV_DEVICES_H
2 #define _RISCV_DEVICES_H
3
4 #include "decode.h"
5 #include <map>
6 #include <vector>
7
8 class processor_t;
9
10 class abstract_device_t {
11 public:
12 virtual bool load(reg_t addr, size_t len, uint8_t* bytes) = 0;
13 virtual bool store(reg_t addr, size_t len, const uint8_t* bytes) = 0;
14 // Return a pointer to the start of the page that addr falls in, or NULL if
15 // there is no IO device at that address.
16 virtual char* page(reg_t addr) { return NULL; }
17 virtual ~abstract_device_t() {}
18 };
19
20 class bus_t : public abstract_device_t {
21 public:
22 bool load(reg_t addr, size_t len, uint8_t* bytes);
23 bool store(reg_t addr, size_t len, const uint8_t* bytes);
24 // Return a pointer to the start of the page that addr falls in, or NULL if
25 // there is no IO device at that address.
26 char* page(reg_t paddr);
27 void add_device(reg_t addr, abstract_device_t* dev);
28
29 private:
30 std::map<reg_t, abstract_device_t*> devices;
31 };
32
33 class rom_device_t : public abstract_device_t {
34 public:
35 rom_device_t(std::vector<char> data);
36 bool load(reg_t addr, size_t len, uint8_t* bytes);
37 bool store(reg_t addr, size_t len, const uint8_t* bytes);
38 const std::vector<char>& contents() { return data; }
39 private:
40 std::vector<char> data;
41 };
42
43 class rtc_t : public abstract_device_t {
44 public:
45 rtc_t(std::vector<processor_t*>&);
46 bool load(reg_t addr, size_t len, uint8_t* bytes);
47 bool store(reg_t addr, size_t len, const uint8_t* bytes);
48 size_t size() { return regs.size() * sizeof(regs[0]); }
49 void increment(reg_t inc);
50 private:
51 std::vector<processor_t*>& procs;
52 std::vector<uint64_t> regs;
53 uint64_t time() { return regs[0]; }
54 };
55
56 #endif